ABC: An Academic Industrial-Strength Verification Tool

  • Robert Brayton
  • Alan Mishchenko
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6174)


ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transformations based on And-Inverter Graphs (AIGs), with a variety of innovative algorithms. A focus on the synergy of sequential synthesis and sequential verification leads to improvements in both domains. This paper introduces ABC, motivates its development, and illustrates its use in formal verification.


Model checking equivalence checking logic synthesis simulation integrated sequential verification flow 


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© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • Robert Brayton
    • 1
  • Alan Mishchenko
    • 1
  1. 1.EECS DepartmentUniversity of CaliforniaBerkeleyUSA

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