A Mechanically Verified AIG-to-BDD Conversion Algorithm

  • Sol Swords
  • Warren A. HuntJr.
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6172)

Abstract

We present the mechanical verification of an algorithm for building a BDD from an AND/INVERTER graph (AIG). The algorithm uses two methods to simplify an input AIG using BDDs of limited size; it repeatedly applies these methods while varying the BDD size limit. One method is similar to dynamic weakening in that it replaces oversized BDDs by a conservative approximation; the other method introduces fresh variables to represent oversized BDDs. This algorithm is written in the executable logic of the ACL2 theorem prover. The primary contribution is the verification of our conversion algorithm. We state its correctness theorem and outline the major steps needed to prove it.

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References

  1. 1.
    Aagaard, M.D., Jones, R.B., Seger, C.-J.H.: Formal verification using parametric representations of boolean constraints. In: Proceedings of the 36th Design Automation Conference, pp. 402–407 (1999)Google Scholar
  2. 2.
    Berman, C.L., Trevillyan, L.H.: Functional comparison of logic designs for VLSI circuits. In: IEEE International Conference on Computer-Aided Design, November 5-9, pp. 456–459 (1989)Google Scholar
  3. 3.
    Boyer, R.S., Hunt Jr, W.A.: Function memoization and unique object representation for ACL2 functions. In: ACL ’06: Proceedings of the sixth international workshop on the ACL2 theorem prover and its applications, pp. 81–89. ACM, New York (2006)CrossRefGoogle Scholar
  4. 4.
    Hazelhurst, S., Seger, C.-J.H.: Symbolic trajectory evaluation. In: Kropf, T. (ed.) Formal Hardware Verification. LNCS, vol. 1287, pp. 3–78. Springer, Heidelberg (1997)Google Scholar
  5. 5.
    Hunt Jr., W.A., Swords, S.: Centaur technology media unit verification. In: Bouajjani, A., Maler, O. (eds.) CAV 2009. LNCS, vol. 5643, pp. 353–367. Springer, Heidelberg (2009)Google Scholar
  6. 6.
    Kaufmann, M., Moore, J.S., Boyer, R.S.: ACL2 version 3.3 (2008), http://www.cs.utexas.edu/~moore/acl2/
  7. 7.
    Kaufmann, M., Moore, J.S., Manolios, P.: Computer-Aided Reasoning: An Approach. Kluwer Academic Publishers, Norwell (2000)Google Scholar
  8. 8.
    Kuehlmann, A., Ganai, M.K., Paruthi, V.: Circuit-based boolean reasoning. In: Proceedings of the 38th Design Automation Conference, pp. 232–237 (2001)Google Scholar
  9. 9.
    Kuehlmann, A., Krohm, F.: Equivalence checking using cuts and heaps. In: Proceedings of the 34th Design Automation Conference, June 9-13, pp. 263–268 (1997)Google Scholar
  10. 10.
    Melham, T.F., Jones, R.B.: Abstraction by symbolic indexing transformations. In: Aagaard, M.D., O’Leary, J.W. (eds.) FMCAD 2002. LNCS, vol. 2517, pp. 1–18. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  11. 11.
    Seger, C.-J.H., Jones, R.B., O’Leary, J.W., Melham, T., Aagaard, M.D., Barrett, C., Syme, D.: An industrially effective environment for formal hardware verification. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24(9), 1381–1405 (2005)CrossRefGoogle Scholar
  12. 12.
    Somenzi, F.: CUDD: CU decision diagram package release 2.4.1 (2005), http://vlsi.colorado.edu/~fabio/CUDD/

Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • Sol Swords
    • 1
  • Warren A. HuntJr.
    • 1
  1. 1.Department of Computer ScienceUniversity of TexasAustin

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