Reducing False Aborts in STM Systems
Transactional memory (TM) continues to be the most promising approach replacing locks in concurrent programming, but TM systems based on software (STM) still lack the desired performance when compared to fine-grained lock implementations. It is known that the critical operation in TM systems is to ensure the atomicity and isolation of concurrently executing threads. This task is known as the read/write-set validation. In attempt to make this process as fast as possible, STM systems usually use ownership tables to perform conflict detection, but this approach generates false positive occurrences, which result in false aborts. This paper shows the real impact of false aborts and how its relevance increases along with the number of concurrent threads, showing it is an essential factor for TM systems. We propose two different techniques to avoid false aborts, showing its benefits and limitations. The first is a collision list attached to the existing hash table. The second is a full associative memory mapping between the addresses and its version information. We achieved significant performance improvements in some STAMP benchmark programs, resulting in speedups up to 1.5x. We also show that speedups become higher when the number of parallel threads increases.
KeywordsHash Table Transactional Memory Collision List Parallel Thread Concurrent Thread
Unable to display preview. Download preview PDF.
- 2.Hammond, L., Wong, V., Chen, M., Carlstrom, B.D., Davis, J.D., Hertzberg, B., Prabhu, M.K., Wijaya, H., Kozyrakis, C., Olukotun, K.: Transactional memory coherence and consistency. In: ISCA 2004: Proceedings of the 31st annual international symposium on Computer architecture, Washington, DC, USA, p. 102. IEEE Computer Society, Los Alamitos (2004)CrossRefGoogle Scholar
- 6.Minh, C.C., Trautmann, M., Chung, J., McDonald, A., Bronson, N., Casper, J., Kozyrakis, C., Olukotun, K.: An effective hybrid transactional memory system with strong isolation guarantees. In: ISCA 2007: Proceedings of the 34th annual international symposium on Computer architecture, pp. 69–80. ACM, New York (2007)CrossRefGoogle Scholar
- 7.Zilles, C., Rajwar, R.: Implications of false conflict rate trends for robust software transactional memory. In: IISWC 2007: Proceedings of the 2007 IEEE 10th International Symposium on Workload Characterization, Washington, DC, USA, pp. 15–24. IEEE Computer Society, Los Alamitos (2007)CrossRefGoogle Scholar
- 8.Xiaoqiang, Z., Lin, P., Lunguo, X.: Lowering conflicts of high contention software transactional memory. In: CSSE 2008: Proceedings of the 2008 International Conference on Computer Science and Software Engineering, Washington, DC, USA, pp. 307–310. IEEE Computer Society, Los Alamitos (2008)CrossRefGoogle Scholar
- 11.Atoofian, E., Baniasadi, A., Coady, Y.: Adaptive read validation in time-based software transactional memory, pp. 152–162 (2009)Google Scholar
- 12.Dice, D., Shalev, O., Shavit, N.: Transactional locking ii. In: Proc. of the 20th Intl. Symp. on Distributed Computing (2006)Google Scholar
- 13.Adl-Tabatabai, A.R., Lewis, B.T., Menon, V., Murphy, B.R., Saha, B., Shpeisman, T.: Compiler and runtime support for efficient software transactional memory. In: PLDI 2006: Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation, pp. 26–37. ACM, New York (2006)CrossRefGoogle Scholar
- 15.Saha, B., Adl-Tabatabai, A.R., Hudson, R.L., Minh, C.C., Hertzberg, B.: Mcrt-stm: a high performance software transactional memory system for a multi-core runtime. In: PPoPP 2006: Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming, pp. 187–197. ACM, New York (2006)CrossRefGoogle Scholar
- 16.Cao Minh, C., Chung, J., Kozyrakis, C., Olukotun, K.: STAMP: Stanford transactional applications for multi-processing. In: IISWC 2008: Proceedings of The IEEE International Symposium on Workload Characterization (September 2008)Google Scholar