Side-Channel Leakage across Borders

  • Jörn-Marc Schmidt
  • Thomas Plos
  • Mario Kirschbaum
  • Michael Hutter
  • Marcel Medwed
  • Christoph Herbst
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6035)

Abstract

More and more embedded devices store sensitive information that is protected by means of cryptography. The confidentiality of this data is threatened by information leakage via side channels like the power consumption or the electromagnetic radiation. In this paper, we show that the side-channel leakage in the power consumption is not limited to the power-supply lines and that any input/output (I/O) pin can comprise secret information. The amount of leakage depends on the design and on the state of the I/O pin. All devices that we examined leaked secret information through their I/O pins. This implies that any I/O pin that is accessible for an adversary could be a security hole. Moreover, we demonstrate that the leakage is neither prevented by transmitter/receiver circuits as they are used in serial interfaces, nor by a galvanic isolation of a chip and its output signals via optocouplers. An adversary that is able to manipulate, for example, the pins of a PC’s I/O port, can attack any device that is connected to this port without being detected from outside.

Keywords

Power Analysis I/O Pin Microcontroller Optocoupler Serial Interface 

References

  1. 1.
    Kocher, P.C., Jaffe, J., Jun, B.: Differential Power Analysis. In: Wiener, M. (ed.) CRYPTO 1999. LNCS, vol. 1666, pp. 388–397. Springer, Heidelberg (1999)Google Scholar
  2. 2.
    Messerges, T.S., Dabbish, E.A., Sloan, R.H.: Investigations of Power Analysis Attacks on Smartcards. In: USENIX Workshop on Smartcard Technology (Smartcard 1999), May 1999, pp. 151–162 (1999)Google Scholar
  3. 3.
    Örs, S.B., Oswald, E., Preneel, B.: Power-Analysis Attacks on FPGAs – First Experimental Results. In: Walter, C.D., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 35–50. Springer, Heidelberg (2003)Google Scholar
  4. 4.
    Hutter, M., Mangard, S., Feldhofer, M.: Power and EM Attacks on Passive 13.56 MHz RFID Devices. In: Paillier, P., Verbauwhede, I. (eds.) CHES 2007. LNCS, vol. 4727, pp. 320–333. Springer, Heidelberg (2007)CrossRefGoogle Scholar
  5. 5.
    Mangard, S., Oswald, E., Popp, T.: Power Analysis Attacks – Revealing the Secrets of Smart Cards. Springer, Heidelberg (2007), ISBN 978-0-387-30857-9 MATHGoogle Scholar
  6. 6.
    Agrawal, D., Archambeault, B., Rao, J.R., Rohatgi, P.: The EM Side-channel(s). In: Kaliski Jr., B.S., Koç, Ç.K., Paar, C. (eds.) CHES 2002. LNCS, vol. 2523, pp. 29–45. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  7. 7.
    Gandolfi, K., Mourtel, C., Olivier, F.: Electromagnetic Analysis: Concrete Results. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 251–261. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  8. 8.
    Tiri, K., Akmal, M., Verbauwhede, I.: A Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand Differential Power Analysis on Smart Cards. In: Proceedings of 28th European Solid-State Circuits Conference - ESSCIRC 2002, Florence, Italy, September 24-26, pp. 403–406. IEEE, Los Alamitos (2002)Google Scholar
  9. 9.
    Tiri, K., Verbauwhede, I.: A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation. In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), Paris, France, February 16-20, vol. 1, pp. 246–251. IEEE Computer Society, Los Alamitos (2004)CrossRefGoogle Scholar
  10. 10.
    Popp, T., Mangard, S.: Masked Dual-Rail Pre-Charge Logic: DPA-Resistance without Routing Constraints. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 172–186. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  11. 11.
    Coron, J.S., Kocher, P.C., Naccache, D.: Statistics and Secret Leakage. In: Frankel, Y. (ed.) FC 2000. LNCS, vol. 1962, pp. 157–173. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  12. 12.
    Shamir, A.: Protecting Smart Cards from Passive Power Analysis with Detached Power Supplies. In: Paar, C., Koç, Ç.K. (eds.) CHES 2000. LNCS, vol. 1965, pp. 71–77. Springer, Heidelberg (2000)CrossRefGoogle Scholar
  13. 13.
    Corsonello, P., Perri, S., Margala, M.: A New Charge-Pump Based Countermeasure Against Differential Power Analysis. In: Proceedings of the 6th International Conference on ASIC (ASICON 2005), vol. 1, pp. 66–69. IEEE, Los Alamitos (2005)CrossRefGoogle Scholar
  14. 14.
    Oren, Y., Shamir, A.: How not to protect pcs from power analysis. Rump Session, Crypto 2006 (August 2006), http://iss.oy.ne.ro/HowNotToProtectPCsFromPowerAnalysis.pdf
  15. 15.
    Plos, T.: Evaluation of the Detached Power Supply as Side-Channel Analysis Countermeasure for Passive UHF RFID Tags. In: Fischlin, M. (ed.) RSA Conference 2009. LNCS, vol. 5473, pp. 444–458. Springer, Heidelberg (2009)CrossRefGoogle Scholar
  16. 16.
    Weste, N.H.E., Eshraghian, K.: Principles of CMOS VLSI Design - A Systems Perspective, 2nd edn. VLSI Systems Series. Addison-Wesley, Reading (1993) (reprinted with corrections October 1994), ISBN 0-201-53376-6Google Scholar
  17. 17.
    Brier, E., Clavier, C., Olivier, F.: Correlation Power Analysis with a Leakage Model. In: Joye, M., Quisquater, J.-J. (eds.) CHES 2004. LNCS, vol. 3156, pp. 16–29. Springer, Heidelberg (2004)Google Scholar
  18. 18.
    Örs, S.B., Gürkaynak, F.K., Oswald, E., Preneel, B.: Power-Analysis Attack on an ASIC AES Implementation. In: Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC 2004), Las Vegas, Nevada, USA, April 5-7, vol. 2, pp. 546–552. IEEE Computer Society, Los Alamitos (2004)CrossRefGoogle Scholar
  19. 19.
    Schramm, K., Leander, G., Felke, P., Paar, C.: A Collision-Attack on AES: Combining Side Channel- and Differential-Attack. In: Joye, M., Quisquater, J.-J. (eds.) CHES 2004. LNCS, vol. 3156, pp. 163–175. Springer, Heidelberg (2004)Google Scholar
  20. 20.
    United Microelectronics Corporation: The United Microelectronics Corporation Website, http://www.umc.com/
  21. 21.
    Faraday Technology Corporation: Faraday FSA0A_C 0.18 μm ASIC Standard Cell Library (2004), http://www.faraday-tech.com.
  22. 22.
    Mangard, S., Aigner, M., Dominikus, S.: A Highly Regular and Scalable AES Hardware Architecture. IEEE Transactions on Computers 52(4), 483–491 (2003)CrossRefGoogle Scholar
  23. 23.
    Wolkerstorfer, J., Oswald, E., Lamberger, M.: An ASIC implementation of the AES SBoxes. In: Preneel, B. (ed.) CT-RSA 2002. LNCS, vol. 2271, pp. 67–78. Springer, Heidelberg (2002)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • Jörn-Marc Schmidt
    • 1
  • Thomas Plos
    • 1
  • Mario Kirschbaum
    • 1
  • Michael Hutter
    • 1
  • Marcel Medwed
    • 1
  • Christoph Herbst
    • 1
  1. 1.Institute for Applied Information Processing and Communications (IAIK)Graz University of TechnologyGrazAustria

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