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Automatic Thermal Network Extraction and Multiscale Electro-Thermal Simulation

  • Massimiliano CulpoEmail author
  • Carlo de Falco
  • Georg Denk
  • Steffen Voigtmann
Conference paper
Part of the Mathematics in Industry book series (MATHINDUSTRY, volume 14)

Abstract

We present a new strategy to perform chip-level electro-thermal simulation. In our approach electrical behaviour of each circuit element is modeled by standard compact models with an added temperature node (1; 2). Mutual heating is accounted for by a 2-D or 3-D diffusion reaction PDE, which is coupled to the electrical network by enforcing instantaneous energy conservation. To cope with the multiscale nature of heat diffusion in VLSI circuit a suitable spatial discretization scheme is adopted which allows for efficient meshing of large domains with details at a much smaller scale. Preliminary numerical results on a realistic test case are included as a validation of the model and of the numerical method.

Keywords

Circuit Element Temperature Node Preliminary Numerical Result Thermal Network Thermal Element 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • Massimiliano Culpo
    • 1
    Email author
  • Carlo de Falco
    • 2
  • Georg Denk
    • 3
  • Steffen Voigtmann
    • 3
  1. 1.Bergische Universität WuppertalWuppertalGermany
  2. 2.Dublin City UniversityDublin 9Ireland
  3. 3.Qimonda AG MunichMunichGermany

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