Abstract
We present a new strategy to perform chip-level electro-thermal simulation. In our approach electrical behaviour of each circuit element is modeled by standard compact models with an added temperature node (1; 2). Mutual heating is accounted for by a 2-D or 3-D diffusion reaction PDE, which is coupled to the electrical network by enforcing instantaneous energy conservation. To cope with the multiscale nature of heat diffusion in VLSI circuit a suitable spatial discretization scheme is adopted which allows for efficient meshing of large domains with details at a much smaller scale. Preliminary numerical results on a realistic test case are included as a validation of the model and of the numerical method.
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Culpo, M., de Falco, C., Denk, G., Voigtmann, S. (2010). Automatic Thermal Network Extraction and Multiscale Electro-Thermal Simulation. In: Roos, J., Costa, L. (eds) Scientific Computing in Electrical Engineering SCEE 2008. Mathematics in Industry(), vol 14. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-12294-1_36
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DOI: https://doi.org/10.1007/978-3-642-12294-1_36
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