Application-Specific Signatures for Transactional Memory in Soft Processors

  • Martin Labrecque
  • Mark Jeffrey
  • J. Gregory Steffan
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5992)

Abstract

As reconfigurable computing hardware and in particular FPGA-based systems-on-chip comprise an increasing number of processor and accelerator cores, supporting sharing and synchronization in a way that is scalable and easy to program becomes a challenge. Transactional memory (TM) is a potential solution to this problem, and an FPGA-based system provides the opportunity to support TM in hardware (HTM). Although there are many proposed approaches to HTM support for ASICs, these do not necessarily map well to FPGAs. In particular in this work we demonstrate that while signature-based conflict detection schemes (essentially bit vectors) should intuitively be a good match to the bit-parallelism of FPGAs, previous schemes result in either unacceptable multicycle stalls, operating frequencies, or false-conflict rates. Capitalizing on the reconfigurable nature of FPGA-based systems, we propose an application-specific signature mechanism for HTM conflict detection. Using both real and projected FPGA-based soft multiprocessor systems that support HTM and implement threaded, shared-memory network packet processing applications, relative to signatures with bit selection we find that our application-specific approach (i) maintains a reasonable operating frequency of 125MHz, (ii) has an area overhead of only 5%, and (iii) achieves a 9% to 71% increase in packet throughput due to reduced false conflicts.

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References

  1. 1.
    Wee, S., Casper, J., Njoroge, N., Tesylar, Y., Ge, D., Kozyrakis, C., Olukotun, K.: A practical FPGA-based framework for novel CMP research. In: Proc. of FPGA 2007, pp. 116–125 (2007)Google Scholar
  2. 2.
    Grinberg, S., Weiss, S.: Investigation of transactional memory using FPGAs. In: Proc. of EEEI 2006, pp. 119–122 (November 2006)Google Scholar
  3. 3.
    Kachris, C., Kulkarni, C.: Configurable transactional memory. In: Proc. of FCCM 2007, pp. 65–72. IEEE Computer Society, Los Alamitos (2007)Google Scholar
  4. 4.
    Ceze, L., Tuck, J., Torrellas, J., Cascaval, C.: Bulk disambiguation of speculative threads in multiprocessors. In: Proc. of ISCA 2006, pp. 227–238 (2006)Google Scholar
  5. 5.
    Sanchez, D., Yen, L., Hill, M.D., Sankaralingam, K.: Implementing signatures for transactional memory. In: Proc. of MICRO 2007, pp. 123–133 (2007)Google Scholar
  6. 6.
    Lockwood, J.W., McKeown, N., Watson, G., Gibb, G., Hartke, P., Naous, J., Raghuraman, R., Luo, J.: NetFPGA - an open platform for gigabit-rate network switching and routing. In: Proc. of MSE 2007, June 3-4 (2007)Google Scholar
  7. 7.
    Yen, L., Bobba, J., Marty, M.R., Moore, K.E., Volos, H., Hill, M.D., Swift, M.M., Wood, D.A.: LogTM-SE: Decoupling hardware transactional memory from caches. In: Proc. of HPCA 2007, pp. 261–272 (2007)Google Scholar
  8. 8.
    Yen, L., Draper, S., Hill, M.: Notary: Hardware techniques to enhance signatures. In: Proc. of Micro 2008, pp. 234–245 (November 2008)Google Scholar
  9. 9.
    Quislant, R., Gutierrez, E., Plata, O.: Improving signatures by locality exploitation for transactional memory. In: Proc. of PACT 2009, pp. 303–312 (2009)Google Scholar
  10. 10.
    Otoo, E.J., Effah, S.: Red-black trie hashing. Carleton University, Tech. Rep. TR-95-03 (1995)Google Scholar
  11. 11.
    Khuller, S., Moss, A., Naor, J.S.: The budgeted maximum coverage problem. Inf. Process. Lett. 70(1), 39–45 (1999)CrossRefMathSciNetMATHGoogle Scholar
  12. 12.
    Labrecque, M., Yiannacouras, P., Steffan, J.G.: Custom code generation for soft processors. In: Proc. of RAAW 2006 (December 2006)Google Scholar
  13. 13.
    Veenstra, J., Fowler, R.: MINT: a front end for efficient simulation of shared-memory multiprocessors. In: Proc. of MASCOTS 1994, pp. 201–207 (January 1994)Google Scholar
  14. 14.
    Labrecque, M., Steffan, J.G.: Fast critical sections via thread scheduling for FPGA-based multithreaded processors. In: Proc. of FPL 2009 (September 2009)Google Scholar
  15. 15.
    Teodorescu, R., Torrellas, J.: Prototyping architectural support for program rollback using FPGAs. In: Proc. of FCCM 2005, pp. 23–32 (April 2005)Google Scholar
  16. 16.
    Aasaraai, K., Moshovos, A.: Towards a viable out-of-order soft core: Copy-free, checkpointed register renaming. In: Proc. of FPL (2009)Google Scholar
  17. 17.
    Cao Minh, C., Chung, J., Kozyrakis, C., Olukotun, K.: STAMP: Stanford transactional applications for multi-processing. In: Proc. of IISWC 2008 (September 2008)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • Martin Labrecque
    • 1
  • Mark Jeffrey
    • 1
  • J. Gregory Steffan
    • 1
  1. 1.Department of Electrical and Computer EngineeringUniversity of TorontoCanada

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