An Analysis of Delay Based PUF Implementations on FPGA

  • Sergey Morozov
  • Abhranil Maiti
  • Patrick Schaumont
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5992)

Abstract

Physical Unclonable Functions promise cheap, efficient, and secure identification and authentication of devices. In FPGA devices, PUFs may be instantiated directly from FPGA fabric components in order to exploit the propagation delay differences of signals caused by manufacturing process variations. Multiple delay based PUF architectures have been proposed. However, we have observed inconsistent results among them. Ring Oscillator PUF works fine, while other delay based PUFs show a significantly lower quality. Rather than proposing complex system level solutions, we focus on the fundamental building blocks of the PUF. In our effort to compare the various delay based PUF architectures, we have closely examined how each architecture maps into the FPGA fabric. Our conclusions are that arbiter and butterfly PUF architectures are ill suited for FPGAs, because delay skew due to routing asymmetry is over 10 times higher than the random variation due to manufacturing process.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • Sergey Morozov
    • 1
  • Abhranil Maiti
    • 1
  • Patrick Schaumont
    • 1
  1. 1.Virginia TechBlacksburgUSA

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