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A Reconfigurable Implementation of the Tate Pairing Computation over GF(2m)

  • Weibo Pan
  • William Marnane
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5992)

Abstract

In this paper the performance of a closed formula implemented in reconfigurable hardware for the Tate pairing Algorithm over the binary field of GF(2 m ) is studied. Using the algorithm improvement of Soonhak Kwon [2], the schedule for performing the Tate pairing without a square root operation is explored along with the area and time consumption trade-offs involved in the hardware implementation of the target algorithm.

Keywords

Tate pairing FPGA implementation 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • Weibo Pan
    • 1
  • William Marnane
    • 1
  1. 1.Dept. of Electrical and Electronic EngineeringUniversity College CorkCork CityIreland

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