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Quasi-Delay-Insensitive Computing Device: Methodological Aspects and Practical Implementation

  • Yuri Stepchenkov
  • Yuri Diachenko
  • Victor Zakharov
  • Yuri Rogdestvenski
  • Nikolai Morozov
  • Dmitri Stepchenkov
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5953)

Abstract

The approaches to self-timed hardware design are presented. The conditions of intersystem integration of synchronous and self-timed devices are considered through the example of the quasi-delay-insensitive computing device development. This device performs functions of division and square root extraction. It operates with numbers of single and double precisions corresponding to the IEEE 754 standard.

Keywords

Self-timed quasi-delay-insensitive division square root Radix-2 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • Yuri Stepchenkov
    • 1
  • Yuri Diachenko
    • 1
  • Victor Zakharov
    • 1
  • Yuri Rogdestvenski
    • 1
  • Nikolai Morozov
    • 1
  • Dmitri Stepchenkov
    • 1
  1. 1.Institute of Informatics ProblemsRussian Academy of SciencesMoscowRussia

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