Speeding-Up Expensive Evaluations in High-Level Synthesis Using Solution Modeling and Fitness Inheritance

  • Christian Pilato
  • Daniele Loiacono
  • Antonino Tumeo
  • Fabrizio Ferrandi
  • Pier Luca Lanzi
  • Donatella Sciuto
Part of the Adaptation Learning and Optimization book series (ALO, volume 2)


High-Level Synthesis (HLS) is the process of developing digital circuits from behavioral specifications. It involves three interdependent and NP-complete optimization problems: (i) the operation scheduling, (ii) the resource allocation, and (iii) the controller synthesis. Evolutionary Algorithms have been already effectively applied to HLS to find good solution in presence of conflicting design objectives. In this paper, we present an evolutionary approach to HLS that extends previous works in three respects: (i) we exploit the NSGA-II, a multi-objective genetic algorithm, to fully automate the design space explorationwithout the need of any human intervention, (ii) we replace the expensive evaluation process of candidate solutions with a quite accurate regression model, and (iii) we reduce the number of evaluations with a fitness inheritance scheme. We tested our approach on several benchmark problems. Our results suggest that all the enhancements introduced improve the overall performance of the evolutionary search.


Linear Regression Model Field Programmable Gate Array Solution Evaluation Design Space Exploration Multiobjective Genetic Algorithm 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Araújo, S.G., Mesquita, A.C., Pedroza, A.: Optimized Datapath Design by Evolutionary Computation. In: IWSOC: International Workshop on System-on-Chip for Real-Time Applications, pp. 6–9 (2003)Google Scholar
  2. 2.
    Barthelemy, J.F.M., Haftka, R.T.: Approximation concepts for optimum structural design - a review. Structural Optimization (5), 129–144 (1993)Google Scholar
  3. 3.
    Brandolese, C., Fornaciari, W., Salice, F.: An area estimation methodology for FPGA based designs at SystemC-level. In: DAC: Design Automation Conference, pp. 129–132. ACM, New York (2004)Google Scholar
  4. 4.
    Chaiyakul, V., Wu, A.C.H., Gajski, D.D.: Timing models for high-level synthesis. In: EURO-DAC 1992: European Design Automation Conference, pp. 60–65. IEEE Computer Society Press, Los Alamitos (1992)CrossRefGoogle Scholar
  5. 5.
    Chen, D., Cong, J.: Register binding and port assignment for multiplexer optimization. In: ASP-DAC: Asia South Pacific Design Automation Conference, pp. 68–73 (2004)Google Scholar
  6. 6.
    Chen, J.H., Goldberg, D.E., Ho, S.Y., Sastry, K.: Fitness inheritance in multi-objective optimization. In: GECCO: Genetic and Evolutionary Computation Conference, pp. 319–326 (2002)Google Scholar
  7. 7.
    Cordone, R., Ferrandi, F., Santambrogio, M.D., Palermo, G., Sciuto, D.: Using speculative computation and parallelizing techniques to improve scheduling of control based designs. In: ASPDAC: Asia South Pacific Design Automation Conference, pp. 898–904. ACM, Yokohama (2006)Google Scholar
  8. 8.
    De Micheli, G.: Synthesis and Optimization of Digital Circuits. McGraw-Hill, New York (1994)Google Scholar
  9. 9.
    Deb, K., Agrawal, S., Pratab, A., Meyarivan, T.: A Fast and Elitist Multi-Objective Genetic Algorithm: NSGA-II. In: Deb, K., Rudolph, G., Lutton, E., Merelo, J.J., Schoenauer, M., Schwefel, H.-P., Yao, X. (eds.) PPSN 2000. LNCS, vol. 1917, pp. 849–858. Springer, Heidelberg (2000)CrossRefGoogle Scholar
  10. 10.
    Dennis, J., Torczon, V.: Managing approximate models in optimization. In: Alexandrov, N., Hussani, M. (eds.) Multidisciplinary design optimization: State-of-the-art, pp. 330–347. SIAM, Philadelphia (1997)Google Scholar
  11. 11.
    Ducheyne, E., Baets, B.D., Wulf, R.D.: Is fitness inheritance useful for real-world applications? (2003)Google Scholar
  12. 12.
    Ferrandi, F., Lanzi, P.L., Palermo, G., Pilato, C., Sciuto, D., Tumeo, A.: An evolutionary approach to area-time optimization of FPGA designs. In: ICSAMOS: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, pp. 145–152 (2007)Google Scholar
  13. 13.
    Grefenstette, J.J., Fitzpatrick, J.M.: Genetic search with approximate function evaluation. In: International Conference on Genetic Algorithms, pp. 112–120. Lawrence Erlbaum Associates, Inc., Mahwah (1985)Google Scholar
  14. 14.
    Grewal, G., O’Cleirigh, M., Wineberg, M.: An evolutionary approach to behavioural-level synthesis. In: CEC: IEEE Congress on Evolutionary Computation, 8-12, pp. 264–272. ACM Press, New York (2003)CrossRefGoogle Scholar
  15. 15.
    Gu, Z., Wang, J., Dick, R.P., Zhou, H.: Unified incremental physicallevel and high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9), 1576–1588 (2007)CrossRefGoogle Scholar
  16. 16.
    Harik, G.: Linkage Learning via ProbabilisticModeling in the ECGA (1999)Google Scholar
  17. 17.
    Huband, S., Hingston, P.: An evolution strategy with probabilistic mutation for multi-objective optimisation. In: IEEE Congress on Evolutionary Computation, CEC 2003, pp. 2284–2291. IEEE Press, Piscataway (2003)CrossRefGoogle Scholar
  18. 18.
    Hwang, C.T., Leea, J.H., Hsu, Y.C.: A formal approach to the scheduling problem in high level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 10(4), 464–475 (1991)CrossRefGoogle Scholar
  19. 19.
    Jin, Y.: A comprehensive survey of fitness approximation in evolutionary computation. Soft Comput. 9(1), 3–12 (2005)CrossRefGoogle Scholar
  20. 20.
    Kollig, P., Al-Hashimi, B.: Simultaneous scheduling, allocation and binding in high level synthesis. Electronics Letters 33(18), 1516–1518 (1997)CrossRefGoogle Scholar
  21. 21.
    Krishnan, V., Katkoori, S.: A genetic algorithm for the design space exploration of datapaths during high-level synthesis. IEEE Trans. Evolutionary Computation 10(3), 213–229 (2006)CrossRefGoogle Scholar
  22. 22.
    Kuehlmann, A., Bergamaschi, R.A.: Timing analysis in high-level synthesis. In: ICCAD: International Conference on Computer-Aided Design, pp. 349–354. IEEE Computer Society Press, Los Alamitos (1992)CrossRefGoogle Scholar
  23. 23.
    Llor‘a, X., Sastry, K., Goldberg, D.E., Gupta, A., Lakshmi, L.: Combating user fatigue in iGAs: partial ordering, support vector machines, and synthetic fitness. In: GECCO: Conference on Genetic and evolutionary computation, pp. 1363–1370. ACM Press, New York (2005)CrossRefGoogle Scholar
  24. 24.
    Mandal, C., Chakrabarti, P.P., Ghose, S.: Design space exploration for data path synthesis. In: International Conf. on VLSI Design, pp. 166–170 (1996)Google Scholar
  25. 25.
    Mandal, C., Chakrabarti, P.P., Ghose, S.: GABIND: a GA approach to allocation and binding for the high-level synthesis of data paths. IEEE Transaction on Very Large Scale Integration System 8(6), 747–750 (2000)CrossRefGoogle Scholar
  26. 26.
    Meribout, M., Motomura, M.: Efficient metrics and high-level synthesis for dynamically reconfigurable logic. IEEE Trans. Very Large Scale Integr. Syst. 12(6), 603–621 (2004)CrossRefGoogle Scholar
  27. 27.
    Palesi, M., Givargis, T.: Multi-objective design space exploration using genetic algorithms. In: CODES: International Symposium on Hardware/ software Codesign, pp. 67–72. ACM, New York (2002)CrossRefGoogle Scholar
  28. 28.
    Paulin, P.G., Knight, J.P.: Force-directed scheduling for the behavioral synthesis of ASICs. IEEE Trans. on CAD of Integrated Circuits and Systems 8(6), 661–679 (1989)CrossRefGoogle Scholar
  29. 29.
    Pilato, C., Palermo, G., Tumeo, A., Ferrandi, F., Sciuto, D., Lanzi, P.L.: Fitness inheritance in evolutionary and multi-objective high-level synthesis. In: IEEE Congress on Evolutionary Computation, pp. 3459–3466 (2007)Google Scholar
  30. 30.
    Reyes-Sierra, M., Coello, C.: A study of fitness inheritance and approximation techniques for multi-objective particle swarm optimization 1, 65–72 (2005)Google Scholar
  31. 31.
    Sastry, K.: Evaluation-relaxation schemes for genetic and evolutionary algorithms. Master’s thesis, General Engineering Department, University of Illinois at Urbana-Champaign, Urbana, IL (2001)Google Scholar
  32. 32.
    Sastry, K., Goldberg, D.E., Pelikan, M.: Don’t evaluate, inherit. In: GECCO: Genetic and Evolutionary Computation Conference, pp. 551–558. Morgan Kaufmann, San Francisco (2001)Google Scholar
  33. 33.
    Sastry, K., Lima, C.F., Goldberg, D.E.: Evaluation relaxation using substructural information and linear estimation. In: GECCO 2006, pp. 419–426. ACM, Seattle (2006)CrossRefGoogle Scholar
  34. 34.
    Smith, R.E., Dike, B.A., Stegmann, S.A.: Fitness inheritance in genetic algorithms. In: SAC: Symposium on Applied computing, pp. 345–350. ACM Press, New York (1995)Google Scholar
  35. 35.
    Stok, L.: Data Path Synthesis. Integration, the VLSI Journal 18(1), 1–71 (1994)zbMATHCrossRefGoogle Scholar
  36. 36.
    Teich, J., Blickle, T., Thiele, L.: An evolutionary approach to system level synthesis. In: CODES Workshop, p. 167 (1997)Google Scholar
  37. 37.
    Wanner, E., Guimaraes, F., Takahashi, R., Fleming, P.: A quadratic approximation-based local search procedure for multiobjective genetic algorithms. In: IEEE Congress on Evolutionary Computation, CEC 2006, pp. 938–945 (2006), doi:10.1109/CEC.2006.1688411Google Scholar
  38. 38.
    Zitzler, E., Optimization, M., Zrich, E.H., Thiele, L., Deb, K.: Evolutionary algorithms for multiobjective optimization: Methods and applications. PhD thesis (1999)Google Scholar
  39. 39.
    Zitzler, E., Deb, K., Thiele, L.: Comparison of multiobjective evolutionary algorithms: Empirical results. Evolutionary Computation 8(2), 173–195 (2000)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • Christian Pilato
    • 1
  • Daniele Loiacono
    • 1
  • Antonino Tumeo
    • 1
  • Fabrizio Ferrandi
    • 1
  • Pier Luca Lanzi
    • 1
  • Donatella Sciuto
    • 1
  1. 1.Dipartimento di Elettronica ed InformazionePolitecnico di Milano 

Personalised recommendations