Abstract

Clever algorithm design is sometimes superseded by simple encodings into logic. We apply this motto to a few case studies in the formal verification of security properties. In particular, we examine confidentiality objectives in hardware circuit descriptions written in VHDL.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2009

Authors and Affiliations

  • Jean Goubault-Larrecq
    • 1
  1. 1.LSVENS Cachan, CNRS, INRIA SaclayCachanFrance

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