Verifying Stateful Timed CSP Using Implicit Clocks and Zone Abstraction

  • Jun Sun
  • Yang Liu
  • Jin Song Dong
  • Xian Zhang
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5885)

Abstract

In this work, we study model checking of compositional real-time systems. A system is modeled using mutable data variables as well as a compositional timed process. Instead of explicitly manipulating clock variables, a number of compositional timed behavioral patterns are used to capture quantitative timing requirements, e.g. delay, timeout, deadline, timed interrupt, etc. A fully automated abstraction technique is developed to build an abstract finite state machine from the model. The idea is to dynamically create/delete clocks, and maintain/solve a constraint on the clocks. The abstract machine weakly bi-simulates the model and, therefore, LTL model checking or trace-refinement checking are sound and complete. We enhance our home-grown PAT model checker with the technique and show its usability via the verification of benchmark systems.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2009

Authors and Affiliations

  • Jun Sun
    • 1
  • Yang Liu
    • 1
  • Jin Song Dong
    • 1
  • Xian Zhang
    • 1
  1. 1.School of ComputingNational University of Singapore 

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