OpenMP Support for NBTI-Induced Aging Tolerance in MPSoCs

  • Andrea Marongiu
  • Andrea Acquaviva
  • Luca Benini
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5873)


Aging effect in next-generation technologies will play a major role in determining system reliability. In particular, wear-out impact due to Negative Bias Temperature Instability (NBTI) will cause an increase in circuit delays of up to 10% in three years [8]. In these systems, NBTI-induced aging can be slowed-down by inserting periods of recovery where the core is functionally idle and gate input is forced to a specific state. This effect can be exploited to impose a given common target lifetime for all the cores. In this paper we present a technique that allows core-wear-out dependent insertion of recovery periods during loop execution in MPSoCs. Performance loss is compensated based on the knowledge of recovery periods. Loop iterations are re-distributed so that cores with longer recovery are allocated less iterations.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Marongiu, A., Benini, L.: Efficient OpenMP support and extensions for MPSoCs with Explicitly managed memory hierarchy. In: DATE 2009: Proceedings of the 12th International Conference on Design, Automation and Test in Europe, pp. 809–814 (2009)Google Scholar
  2. 2.
    Agarwal, M., Paul, B., Zhang, M., Mitra, S.: Circuit failure prediction and its application to transistor aging. In: Proceedings of the 25th IEEE VLSI Test Symposium table of contents, pp. 277–286 (2007)Google Scholar
  3. 3.
    Dorta, A.J., Rodriguez, C., de Sande, F.: The OpenMP source code repository. In: 13th Euromicro Conference on Parallel, Distributed and Network-Based Processing, PDP 2005, pp. 244–250 (2005)Google Scholar
  4. 4.
    Eireiner, M., Henzler, S., Georgakos, G., Berthold, J., Schmitt-Landsiedel, D.: In-situ delay characterization and local supply voltage adjustment for compensation of local parametric variations. IEEE Journal of Solid-State Circuits 42(7), 1583–1592 (2007)CrossRefGoogle Scholar
  5. 5.
    Hong, S., Narayanan, S., Kandemir, M., Ozturk, O.: Process variation aware thread mapping for chip multiprocessors. In: DATE 2009: Proceedings of the 12th International Conference on Design, Automation and Test in Europe, pp. 821–826 (2009)Google Scholar
  6. 6.
  7. 7.
    Jeun, W.-C., Ha, S.: Effective OpenMP implementation and translation for multiprocessor system-on-chip without using OS. In: Asia and South Pacific Design Automation Conference, ASP-DAC 2007, pp. 44–49 (2007)Google Scholar
  8. 8.
    Kang, K., Park, S.P., Roy, K., Alam, M.A.: Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance. In: ICCAD 2007: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, pp. 730–734 (2007)Google Scholar
  9. 9.
    Karl, E., Blaauw, D., Sylvester, D., Mudge, T.: Multi-mechanism reliability modeling and management in dynamic systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16(4), 476–487 (2008)CrossRefGoogle Scholar
  10. 10.
    Krishnan, A., Reddy, V., Chakravarthi, S., Rodriguez, J., John, S., Krishnan, S.: NBTI impact on transistor and circuit: models, mechanisms and scaling effects. In: Technical Digest. IEEE International Electron Devices Meeting, IEDM 2003, pp. 14.5.1–14.5.4 (2003)Google Scholar
  11. 11.
    Kumar, S.V., Kim, C.H., Sapatnekar, S.S.: An analytical model for negative bias temperature instability. In: ICCAD 2006: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, pp. 493–496 (2006)Google Scholar
  12. 12.
    Liu, F., Chaudhary, V.: Extending OpenMP for heterogeneous chip multiprocessors. In: 2003 International Conference on Parallel Processing, 2003. Proceedings, pp. 161–168 (2003)Google Scholar
  13. 13.
    Liu, F., Chaudhary, V.: A practical OpenMP compiler for system on chips. In: Voss, M.J. (ed.) WOMPAT 2003. LNCS, vol. 2716, pp. 54–68. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  14. 14.
    O’Brien, K., O’Brien, K., Sura, Z., Chen, T., Zhang, T.: Supporting OpenMP on cell. In: Chapman, B., Zheng, W., Gao, G.R., Sato, M., Ayguadé, E., Wang, D. (eds.) IWOMP 2007. LNCS, vol. 4935, pp. 65–76. Springer, Heidelberg (2008)CrossRefGoogle Scholar
  15. 15.
    Roberts, D., Dreslinski, R.G., Karl, E., Mudge, T., Sylvester, D., Blaauw, D.: When homogeneous becomes heterogeneous. In: Third workshop on Operating Systems for Heterogeneous Multiprocessor Architectures, OSHMA (2007)Google Scholar
  16. 16.
    Tiwari, A., Torrellas, J.: Facelift: Hiding and slowing down aging in multicores. In: 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 129–140 (2008)Google Scholar
  17. 17.
    Wang, F., Nicopoulos, C., Wu, X., Xie, Y., Vijaykrishnan, N.: Variation-aware task allocation and scheduling for MPSoC. In: ICCAD 2007: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, pp. 598–603 (2007)Google Scholar
  18. 18.
    Winter, J., Albonesi, D.: Scheduling algorithms for unpredictably heterogeneous CMP architectures. In: 38th International Conference on Dependable Systems and Networks, pp. 42–51 (2008)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2009

Authors and Affiliations

  • Andrea Marongiu
    • 1
  • Andrea Acquaviva
    • 2
  • Luca Benini
    • 1
  1. 1.DEISUniversity of BolognaBolognaItaly
  2. 2.DAUINPolitecnico di TorinoTorinoItaly

Personalised recommendations