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Monitor Circuits for LTL with Bounded and Unbounded Future

  • Bernd Finkbeiner
  • Lars Kuhtz
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5779)

Abstract

Synthesizing monitor circuits for LTL formulas is expensive, because the number of flip-flops in the circuit is exponential in the length of the formula. As a result, the IEEE standard PSL recommends to restrict monitoring to the simple subset and use the full logic only for static verification. We present a novel construction for the synthesis of monitor circuits from specifications in LTL. In our construction, only subformulas with unbounded-future operators contribute to the exponential blowup. We split the specification into a bounded and an unbounded part, apply specialized constructions for each part, and then compose the results into a monitor for the original specification. Since the unbounded part in practical specifications is often very small, we argue that, with the new construction, it is no longer necessary to restrict runtime verification to the simple subset.

Keywords

State Machine Model Check Atomic Proposition Boolean Expression Input Word 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Kupferman, O., Vardi, M.: Model checking of safety properties. In: Halbwachs, N., Peled, D.A. (eds.) CAV 1999. LNCS, vol. 1633, pp. 172–183. Springer, Heidelberg (1999)CrossRefGoogle Scholar
  2. 2.
    IEEE Std 1850-2007: Standard for Property Specification Language (PSL). IEEE, New York (2007)Google Scholar
  3. 3.
    Cohen, B., Venkataramanan, S., Kumari, A.: Using PSL/Sugar for Formal and Dynamic Verification. VhdlCohen Publishing, Los Angeles (2004)Google Scholar
  4. 4.
    Kleene, S.: Representation of events in nerve nets and finite automata. In: Automata Studies. Princeton University Press, Princeton (1956)Google Scholar
  5. 5.
    McNaughton, R., Papert, S.: Counter-Free Automata. Research Monograph, vol. 65. MIT Press, Cambridge (1971)zbMATHGoogle Scholar
  6. 6.
    Eisner, C., Fisman, D., Havlicek, J., Lustig, Y., McIsaac, A., Campenhout, D.V.: Reasoning with temporal logic on truncated paths. In: Hunt Jr., W.A., Somenzi, F. (eds.) CAV 2003. LNCS, vol. 2725, pp. 27–39. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  7. 7.
    Finkbeiner, B., Sipma, H.B.: Checking finite traces using alternating automata. In: Havelund, K., Roşu, G. (eds.) Runtime Verification 2001. Electronic Notes in Theoretical Computer Science, vol. 55, pp. 44–60. Elsevier, Amsterdam (2001)Google Scholar
  8. 8.
    Geilen, M.: On the construction of monitors for temporal logic properties. Electr. Notes Theor. Comput. Sci. 55(2) (2001)Google Scholar
  9. 9.
    Giannakopoulou, D., Havelund, K.: Automata-based verification of temporal properties on running programs. In: ASE, pp. 412–416. IEEE Computer Society, Los Alamitos (2001)Google Scholar
  10. 10.
    Havelund, K., Rosu, G.: Monitoring programs using rewriting. In: ASE, pp. 135–143. IEEE Computer Society, Los Alamitos (2001)Google Scholar
  11. 11.
    Bauer, A., Leucker, M., Schallhart, C.: The good, the bad, and the ugly, but how ugly is ugly? In: Sokolsky, O., Taşıran, S. (eds.) RV 2007. LNCS, vol. 4839, pp. 126–138. Springer, Heidelberg (2007)CrossRefGoogle Scholar
  12. 12.
    Dahan, A., Geist, D., Gluhovsky, L., Pidan, D., Shapir, G., Wolfsthal, Y., Benalycherif, L., Kamdem, R., Lahbib, Y.: Combining system level modeling with assertion based verification. In: ISQED 2005, pp. 310–315. IEEE Comp. Soc., Los Alamitos (2005)Google Scholar
  13. 13.
    Boule, M., Zilic, Z.: Automata-based assertion-checker synthesis of PSL properties. ACM Transactions on Design Automation of Electronic Systems (TODAES) 13(1) (2008)Google Scholar
  14. 14.
    Armoni, R., Korchemny, D., Tiemeyer, A., Vardi, M.Y., Zbar, Y.: Deterministic dynamic monitors for linear-time assertions. In: Havelund, K., Núñez, M., Roşu, G., Wolff, B. (eds.) FATES 2006 and RV 2006. LNCS, vol. 4262, pp. 163–177. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  15. 15.
    Ruah, S., Fisman, D., Ben-David, S.: Automata construction for on-the-fly model checking PSL safety simple subset. Technical report, IBM Research (2005)Google Scholar
  16. 16.
    Ben-David, S., Bloem, R., Fisman, D., Griesmayer, A., Pill, I., Ruah, S.: Automata construction algorithm optimized for PSL. Technical report, PROSYD (July 2005)Google Scholar
  17. 17.
    Pnueli, A., Zaks, A.: PSL model checking and run-time verification via testers. In: Misra, J., Nipkow, T., Sekerinski, E. (eds.) FM 2006. LNCS, vol. 4085, pp. 573–586. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  18. 18.
    Cimatti, A., Roveri, M., Semprini, S., Tonetta, S.: From PSL to NBA: a modular symbolic encoding. In: FMCAD 2006: Proceedings of the Formal Methods in Computer Aided Design, Washington, DC, USA, pp. 125–133. IEEE Computer Society, Los Alamitos (2006)CrossRefGoogle Scholar
  19. 19.
    Ben-David, S., Fisman, D., Ruah, S.: The safety simple subset. In: Ur, S., Bin, E., Wolfsthal, Y. (eds.) HVC 2005. LNCS, vol. 3875, pp. 14–29. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  20. 20.
    d’Amorim, M., Rosu, G.: Efficient monitoring of omega-languages. In: Etessami, K., Rajamani, S.K. (eds.) CAV 2005. LNCS, vol. 3576, pp. 364–378. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  21. 21.
    Brzozowski, J., Simon, I.: Characterizations of locally testable events. Discrete Math. 4, 243–271 (1973)MathSciNetCrossRefzbMATHGoogle Scholar
  22. 22.
    Wike, T.: Locally threshold testable languages of infinite words. In: Enjalbert, P., Wagner, K.W., Finkel, A. (eds.) STACS 1993. LNCS, vol. 665, pp. 607–616. Springer, Heidelberg (1993)CrossRefGoogle Scholar
  23. 23.
    Kupferman, O., Lustig, Y., Vardi, M.: On locally checkable properties. In: Hermann, M., Voronkov, A. (eds.) LPAR 2006. LNCS (LNAI), vol. 4246, pp. 302–316. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  24. 24.
    Etessami, K., Holzmann, G.: Optimizing Büchi automata. In: Palamidessi, C. (ed.) CONCUR 2000. LNCS, vol. 1877, pp. 153–167. Springer, Heidelberg (2000)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2009

Authors and Affiliations

  • Bernd Finkbeiner
    • 1
  • Lars Kuhtz
    • 1
  1. 1.Universität des SaarlandesSaarbrückenGermany

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