Automatic Generation of Cycle-Approximate TLMs with Timed RTOS Model Support

  • Yonghyun Hwang
  • Gunar Schirner
  • Samar Abdi
Part of the IFIP Advances in Information and Communication Technology book series (IFIPAICT, volume 310)


This paper presents a technique for automatically generating cycle-approximate transaction level models (TLMs) for multi-process applications mapped to embedded platforms. It incorporates three key features: (a) basic block level timing annotation, (b) RTOS model integration, and (c) RTOS overhead delay modeling. The inputs to TLM generation are application C processes and their mapping to processors in the platform. A processor data model, including pipelined datapath, memory hierarchy and branch delay model is used to estimate basic block execution delays. The delays are annotated to the C code, which is then integrated with a generated SystemC RTOS model. Our abstract RTOS provides dynamic scheduling and inter-process communication (IPC) with processor- and RTOS-specific pre-characterized timing. Our experiments using a MP3 decoder and a JPEG encoder show that timed TLMs, with integrated RTOS models, can be automatically generated in less than a minute. Our generated TLMs simulated three times faster than real-time and showed less than 10% timing error compared to board measurements.


Transaction Level Modeling Timed RTOS Modeling 


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Copyright information

© IFIP International Federation for Information Processing 2009

Authors and Affiliations

  • Yonghyun Hwang
    • 1
  • Gunar Schirner
    • 2
  • Samar Abdi
    • 3
  1. 1.University of CaliforniaIrvineUSA
  2. 2.Northeastern UniversityBostonUSA
  3. 3.Concordia UniversityMontrealCanada

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