A Real-Time Occlusion Aware Hardware Structure for Disparity Map Computation

  • Christos Georgoulas
  • Ioannis Andreadis
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5716)


Many machine vision applications deal with depth estimation in a scene. Disparity map recovery from a stereo image pair has been extensively studied by the computer vision community. Previous methods are mainly restricted to software based techniques on general-purpose architectures, presenting relatively high execution time due to the computationally complex algorithms involved. In this paper a new hardware module suitable for real-time disparity map computation module is realized. This enables a hardware based occlusion-aware parallel-pipelined design, implemented on a single FPGA device with a typical operating frequency of 511 MHz. It provides accurate disparity map computation at a rate of 768 frames per second, given a stereo image pair with a disparity range of 80 pixels and 640x480 pixel spatial resolution. The proposed method allows a fast disparity map computational module to be built, enabling a suitable module for real-time stereo vision applications.


FPGA-hardware implementation occlusions real–time imaging disparity maps color image processing 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2009

Authors and Affiliations

  • Christos Georgoulas
    • 1
  • Ioannis Andreadis
    • 1
  1. 1.Laboratory of Electronics Department of Electrical and Computer EngineeringDemocritus University of ThraceXanthiGreece

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