Hybrid Techniques for Fast Multicore Simulation

  • Manu Shantharam
  • Padma Raghavan
  • Mahmut Kandemir
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5704)


One of the challenges in the design of multicore architectures concerns the fast evaluation of hardware design-tradeoffs using simulation techniques. Simulation tools for multicore architectures tend to have long execution times that grow linearly with the number of cores simulated. In this paper, we present two hybrid techniques for fast and accurate multicore simulation. Our first method, the Monte Carlo Co-Simulation (MCCS) scheme, considers application phases, and within each phase, interleaves a Monte Carlo modeling scheme with a traditional simulator, such as Simics. Our second method, the Curve Fitting Based Simulation (CFBS) scheme, is tailored to evaluate the behavior of applications with multiple iterations, such as scientific applications that have consistent cycles per instruction (CPI) behavior within a subroutine over different iterations. In our CFBS method, we represent the CPI profile of a subroutine as a signature using curve fitting and represent the entire application execution as a set of signatures to predict performance metrics. Our results indicate that MCCS can reduce simulation time by as much as a factor of 2.37, with a speedup of 1.77 on average compared to Simics. We also observe that CFBS can reduce simulation time by as much as a factor of 13.6, with a speedup of 6.24 on average. The observed average relative errors in CPI compared to Simics are 32% for MCCS and significantly lower, at 2%, for CFBS.


Hybrid Technique Average Relative Error Step Number Instruction Type Multicore Architecture 
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  1. 1.
    From a few cores to many: A tera-scale computing research overview. Technical report, IntelGoogle Scholar
  2. 2.
  3. 3.
    Austin, T., Larson, E., Ernst, D.: Simplescalar: An infrastructure for computer system modeling. Computer 35(2), 59–67 (2002)CrossRefGoogle Scholar
  4. 4.
    Perelman, E., et al.: Using simpoint for accurate and efficient simulation. SIGMETRICS Perform. Eval. Rev. 31(1), 318–319 (2003)CrossRefGoogle Scholar
  5. 5.
    Renau, J., et al.: SESC simulator (January 2005),
  6. 6.
    Lauterbach, et al.: Ultrasparc-iii: a 3rd generation 64 b sparc microprocessor. In: ISSCC 2000. IEEE International on Solid-State Circuits Conference, 2000. Digest of Technical Papers., pp. 410–411 (2000)Google Scholar
  7. 7.
    Rosenblum, M., et al.: Complete computer system simulation: the simos approach. IEEE Parallel and Distributed Technology: Systems and Applications 3(4), 34–43 (Winter 1995)CrossRefGoogle Scholar
  8. 8.
    Oskin, M., et al.: Hls: combining statistical and symbolic simulation to guide microprocessor designs. SIGARCH Comput. Archit. News 28(2), 71–82 (2000)CrossRefGoogle Scholar
  9. 9.
    Martin, M.M.K., et al.: Multifacet’s general execution-driven multiprocessor simulator (gems) toolset. SIGARCH Comput. Archit. News 33(4), 92–99 (2005)MathSciNetCrossRefGoogle Scholar
  10. 10.
    Magnusson, P.S., et al.: Simics: A full system simulation platform. Computer 35(2), 50–58 (2002)CrossRefGoogle Scholar
  11. 11.
    Wunderlich, R.E., et al.: Smarts: accelerating microarchitecture simulation via rigorous statistical sampling. SIGARCH Comput. Archit. News 31(2), 84–97 (2003)CrossRefGoogle Scholar
  12. 12.
    Woo, S.C., et al.: The splash-2 programs: characterization and methodological considerations. In: ISCA 1995: Proceedings of the 22nd annual international symposium on Computer architecture, pp. 24–36 (1995)Google Scholar
  13. 13.
    Wenisch, T.F., et al.: Simflex: Statistical sampling of computer system simulation. IEEE Micro. 26(4), 18–31 (2006)CrossRefGoogle Scholar
  14. 14.
    Sherwood, T., et al.: Automatically characterizing large scale program behavior. In: ASPLOS-X: Proceedings of the 10th international conference on Architectural support for programming languages and operating systems, pp. 45–57. ACM, New York (2002)Google Scholar
  15. 15.
    Heath, M.T.: Scientific computing: An introductory survey (2002)Google Scholar
  16. 16.
    Huang, J., Lilja, D.: An efficient strategy for developing a simulator for a novel concurrent multithreaded processor architecture. In: MASCOTS 1998: Proceedings of the 6th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, Washington, DC, USA, p. 185. IEEE Computer Society, Los Alamitos (1998)Google Scholar
  17. 17.
    Kahle, J.: The cell processor architecture. In: MICRO 38: Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture, p. 3 (2005)Google Scholar
  18. 18.
  19. 19.
    Pai, V.S., Ranganathan, P., Adve, S.V.: Rsim: Rice simulator for ilp multiprocessors. SIGARCH Comput. Archit. News 25(5), 1 (1997)CrossRefGoogle Scholar
  20. 20.
    Intel Core Duo processor Frequently Asked Questions,
  21. 21.
    UltraSPARC T1 Niagara Specifications,
  22. 22.
    Srinivasan, R., Cook, J., Lubeck, O.: Ultra-fast cpu performance prediction: Extending the monte carlo approach. In: SBAC-PAD 2006: Proceedings of the 18th International Symposium on Computer Architecture and High Performance Computing, Washington, DC, USA, pp. 107–116. IEEE Computer Society, Los Alamitos (2006)Google Scholar
  23. 23.
    Srinivasan, R., Lubeck, O.: Montesim: a monte carlo performance model for in-order microachitectures. SIGARCH Comput. Archit. News 33(5), 75–80 (2005)CrossRefGoogle Scholar
  24. 24.
    Yourst, M.T.: Ptlsim: A cycle accurate full system x86-64 microarchitectural simulator. In: IEEE International Symposium on Performance Analysis of Systems Software, 2007. ISPASS 2007, April 2007, pp. 23–34 (2007)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2009

Authors and Affiliations

  • Manu Shantharam
    • 1
  • Padma Raghavan
    • 1
  • Mahmut Kandemir
    • 1
  1. 1.Department of Computer Science & EngineeringPennsylvania State UniversityUSA

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