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Reconfigurable Multicore Server Processors for Low Power Operation

  • Ronald G. Dreslinski
  • David Fick
  • David Blaauw
  • Dennis Sylvester
  • Trevor Mudge
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5657)

Abstract

With power becoming a key design constraint, particularly in server machines, emerging architectures need to leverage reconfigurable techniques to provide an energy optimal system. The need for a single chip solution to fit all needs in a warehouse sized server is important for designers. This allows for simpler design, ease of programmability, and part reuse in all segments of the server. A reconfigurable design would allow a single chip to operate efficiently in all aspects of a server providing both single thread performance for tasks requiring it, and efficient parallel processing helping to reduce power consumption. In this paper we explore the possibility of a reconfigurable server part and discuss the benefits and open questions still surrounding these techniques.

Keywords

Reconfigurable Low Power Server Architectures 

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References

  1. 1.
    Lim, K., Ranganathan, P., Chang, J., Patel, C., Mudge, T., Reinhardt, S.: Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments. In: Proceedings of the 35th ISCA, pp. 315–326 (2008)Google Scholar
  2. 2.
    Report to Congress on Server and Data Center Energy Efficiency, US Environmental ProtectionAgency, http://www.energystar.gov/ia/partners/prod_development/downloads/EPA_Datacenter_Report_Congress_Final1.pdf
  3. 3.
    Zhai, B., Dreslinski, R.G., Mudge, T., Blaauw, D., Sylvester, D.: Energy efficient near-threshold chip multi-processing. In: ACM/IEEE ISLPED, pp. 32–37 (2007)Google Scholar
  4. 4.
    Zhai, B., Blaauw, D., Sylvester, D., Flautner, K.: Theoretical and practical limits of dynamic voltage scaling. In: ACM/IEEE Design Automation Conference, pp. 868–873 (2004)Google Scholar
  5. 5.
    Wang, A., Chandrakasan, A.: A 180mV FFT processor using subthreshold circuit techniques. In: IEEE International Solid-State Circuits Conference, pp. 292–529 (2004)Google Scholar
  6. 6.
    Dreslinski, R.G., Zhai, B., Mudge, T., Blaauw, D., Sylvester, D.: An Energy Efficient Parallel Architecture Using Near Threshold Operation. In: Proceedings of the 16th PACT, pp. 175–188 (2007)Google Scholar
  7. 7.
    Binkert, N.L., Dreslinski, R.G., Hsu, L.R., Lim, K.T., Saidi, A.G., Reinhardt, S.K.: The M5 Simulator: Modeling Networked Systems. IEEE Micro. 26(4), 52–60 (2006)CrossRefGoogle Scholar
  8. 8.
    SpecWeb99 benchmark, http://www.spec.org/web99

Copyright information

© IFIP International Federation for Information Processing 2009

Authors and Affiliations

  • Ronald G. Dreslinski
    • 1
  • David Fick
    • 1
  • David Blaauw
    • 1
  • Dennis Sylvester
    • 1
  • Trevor Mudge
    • 1
  1. 1.Advanced Computer Architecture LabratoryUniversity of MichiganAnn Arbor

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