Software Transactional Memory on Relaxed Memory Models

  • Rachid Guerraoui
  • Thomas A. Henzinger
  • Vasu Singh
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5643)

Abstract

Pseudo-code descriptions of STMs assume sequentially consistent program execution and atomicity of high-level STM operations like read, write, and commit. These assumptions are often violated in realistic settings, as STM implementations run on relaxed memory models, with the atomicity of operations as provided by the hardware. This paper presents the first approach to verify STMs under relaxed memory models with atomicity of 32 bit loads and stores, and read-modify-write operations. We present RML, a new high-level language for expressing concurrent algorithms with a hardware-level atomicity of instructions, and whose semantics is parametrized by various relaxed memory models. We then present our tool, FOIL, which takes as input the RML description of an STM algorithm and the description of a memory model, and automatically determines the locations of fences, which if inserted, ensure the correctness of the STM algorithm under the given memory model. We use FOIL to verify DSTM, TL2, and McRT STM under the memory models of sequential consistency, total store order, partial store order, and relaxed memory order.

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References

  1. 1.
    Adve, S.V., Gharachorloo, K.: Shared memory consistency models: A tutorial. IEEE Computer 29(12), 66–76 (1996)CrossRefGoogle Scholar
  2. 2.
    Burckhardt, S., Alur, R., Martin, M.M.K.: CheckFence: Checking consistency of concurrent data types on relaxed memory models. In: PLDI, pp. 12–21. ACM, New York (2007)Google Scholar
  3. 3.
    Cohen, A., Pnueli, A., Zuck, L.D.: Mechanical verification of transactional memories with non-transactional memory accesses. In: Gupta, A., Malik, S. (eds.) CAV 2008. LNCS, vol. 5123, pp. 121–134. Springer, Heidelberg (2008)CrossRefGoogle Scholar
  4. 4.
    Dice, D., Shalev, O., Shavit, N.: Transactional locking II. In: Dolev, S. (ed.) DISC 2006. LNCS, vol. 4167, pp. 194–208. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  5. 5.
    Emerson, E.A., Sistla, A.P.: Symmetry and model checking. In: Formal Methods in System Design, pp. 105–131 (1996)Google Scholar
  6. 6.
    Guerraoui, R., Henzinger, T.A., Jobstmann, B., Singh, V.: Model checking transactional memories. In: PLDI, pp. 372–382. ACM, New York (2008)CrossRefGoogle Scholar
  7. 7.
    Guerraoui, R., Henzinger, T.A., Singh, V.: Nondeterminism and completeness in transactional memories. In: van Breugel, F., Chechik, M. (eds.) CONCUR 2008. LNCS, vol. 5201, pp. 21–35. Springer, Heidelberg (2008)CrossRefGoogle Scholar
  8. 8.
    Guerraoui, R., Kapalka, M.: On the correctness of transactional memory. In: PPoPP, pp. 175–184. ACM, New York (2008)CrossRefGoogle Scholar
  9. 9.
    Henzinger, T.A., Qadeer, S., Rajamani, S.K.: Verifying sequential consistency on shared-memory multiprocessor systems. In: Halbwachs, N., Peled, D.A. (eds.) CAV 1999. LNCS, vol. 1633, pp. 301–315. Springer, Heidelberg (1999)CrossRefGoogle Scholar
  10. 10.
    Herlihy, M., Luchangco, V., Moir, M., Scherer, W.N.: Software transactional memory for dynamic-sized data structures. In: PODC, pp. 92–101. ACM, New York (2003)Google Scholar
  11. 11.
    Herlihy, M., Moss, J.E.B.: Transactional memory: Architectural support for lock-free data structures. In: ISCA, pp. 289–300. ACM, New York (1993)Google Scholar
  12. 12.
    Lamport, L.: How to make a multiprocessor computer that correctly executes multiprocess programs. IEEE Trans. Computers 28(9), 690–691 (1979)CrossRefMATHGoogle Scholar
  13. 13.
    Lamport, L.: The \(^{\mbox{+}}\)CAL algorithm language. In: Najm, E., Pradat-Peyre, J.-F., Donzeau-Gouge, V.V. (eds.) FORTE 2006. LNCS, vol. 4229, p. 23. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  14. 14.
    Lee, J., Padua, D.A.: Hiding relaxed memory consistency with a compiler. IEEE Trans. Computers 50(8), 824–833 (2001)CrossRefGoogle Scholar
  15. 15.
    Manovit, C., Hangal, S., Chafi, H., McDonald, A., Kozyrakis, C., Olukotun, K.: Testing implementations of transactional memory. In: PACT, pp. 134–143 (2006)Google Scholar
  16. 16.
    Manson, J., Pugh, W., Adve, S.V.: The Java memory model. In: POPL, pp. 378–391. ACM, New York (2005)Google Scholar
  17. 17.
    Papadimitriou, C.H.: The serializability of concurrent database updates. Journal of the ACM 26(4) (1979)Google Scholar
  18. 18.
    Saha, B., Adl-Tabatabai, A., Hudson, R.L., Minh, C.C., Hertzberg, B.: McRT-STM: A high performance software transactional memory system for a multi-core runtime. In: PPOPP, pp. 187–197. ACM, New York (2006)Google Scholar
  19. 19.
    Shavit, N., Touitou, D.: Software transactional memory. In: PODC, pp. 204–213. ACM, New York (1995)Google Scholar
  20. 20.
    Weaver, D., Germond, T. (eds.): The SPARC Architecture Manual (version 9). Prentice-Hall, Inc., Englewood Cliffs (1994)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2009

Authors and Affiliations

  • Rachid Guerraoui
    • 1
  • Thomas A. Henzinger
    • 1
  • Vasu Singh
    • 1
  1. 1.EPFLSwitzerland

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