Workcraft – A Framework for Interpreted Graph Models
A large number of models that are employed in the field of concurrent systems design, such as Petri Nets, gate-level circuits, Static Data Flow Structures and Conditional Partial Order Graphs have an underlying static graph structure. Their semantics, however, is defined using additional entities, e.g. tokens or node/arc states, which in turn form the overall state of the system. We jointly refer to such formalisms as Interpreted Graph Models. The similarities in notation allow for links between different models to be created, such as interfaces between different formalisms or conversion from one model type into another, which greatly extend the range of applicable analysis techniques.
This paper presents the new version of the Workcraft tool designed to provide a flexible common framework for development of Interpreted Graph Models, including visual editing, (co-)simulation and analysis. The latter can be carried out either directly or by mapping a model into a behaviourally equivalent model of a different type (usually a Petri Net). Hence the user can design a system using the most appropriate formalism (or even different formalisms for the subsystems), while still utilising the power of Petri Net analysis techniques. The tool is platform-independent, highly customisable by means of plug-ins, and is freely available for academic use.
KeywordsModel Check Combinational Logic Logic Node Asynchronous Circuit Additional Entity
Unable to display preview. Download preview PDF.
- 1.Ampalam, M., Singh, M.: Counterflow pipelining: architectural support for preemption in asynchronous systems using anti-tokens. In: Proc. CAD 2006 (2006)Google Scholar
- 2.Bardsley, A., Edwards, D.: The Balsa asynchronous circuit synthesis system. In: Forum on Design Languages (2000)Google Scholar
- 3.Clarke, E.M., Grumberg, O., Peled, D.A.: Model Checking. MIT Press, Cambridge (1999)Google Scholar
- 4.Cortadella, J., Kishinevsky, M., Kondratyev, A., Lavagno, L., Yakovlev, A.: Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers. IEICE Trans. Inf. and Syst. E80-D(3), 315–325 (1997)Google Scholar
- 5.Golubcovs, S., Mokhov, A., Yakovlev, A.: Multi-resource Arbiter Design. In: Proc. 20th UK Asynchronous Forum (2008)Google Scholar
- 6.Khomenko, V.: Model Checking Based on Prefixes of Petri Net Unfoldings. PhD thesis, School of Computing Science, Newcastle University (2003)Google Scholar
- 8.Kishinevsky, M.A., Kondratyev, A.Y., Taubin, A.R., Varshavsky, V.I.: On self-timed behavior verification. In: ACM Intl. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (1992)Google Scholar
- 9.Mokhov, A., Yakovlev, A.: Conditional Partial Order Graphs and Dynamically Reconfigurable Control Synthesis. In: Proc. DATE 2008 (2008)Google Scholar
- 10.Pep homepage, http://theoretica.informatik.uni-oldenburg.de/~pep/
- 11.Poliakov, I., Mokhov, A., Rafiev, A., Sokolov, D., Yakovlev, A.: Automated verification of asynchronous circuits using circuit Petri nets. In: Proc. ASYNC 2008, pp. 161–170. IEEE Computer Society, Los Alamitos (2008)Google Scholar
- 13.Roig, O.: Formal Verification and Testing of Asynchronous Circuits. PhD thesis, Universitat Politecnica de Catalunya (1997)Google Scholar
- 14.Sokolov, D., Poliakov, I., Yakovlev, A.: Asynchronous data path models. In: Proc. ACSD 2007 (2007)Google Scholar