Evolutionary Optimization of Number of Gates in PLA Circuits Implemented in VLSI Circuits

  • Adam Slowik
  • Jacek M. Zurada
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5484)

Abstract

In the paper a possibility of evolutionary number of gate optimization in PLA circuits implemented in VLSI technology is presented. Multi-layer chromosomes and specialized genetic operators cooperating to them are introduced to proposed evolutionary algorithm. Due to multi-layer chromosome structures whole gates are transferred in the logic array without disturb in their structures during crossover operation. Results obtained in optimization of gate number in selection boxes of DES cryptographic algorithm are compared to results obtained using SIS program with different optimization scripts such as: rugged, algebraic, and boolean. Proposed method allows to reduce the gates number in optimized circuit. Results obtained using described evolutionary method are better than using other methods.

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References

  1. 1.
    Michalewicz, Z.: Genetic Algorithms + Data Structures = Evolution Programs. Springer, Heidelberg (1992)CrossRefMATHGoogle Scholar
  2. 2.
    Miller, J., Kalganova, T., Lipnitskaya, N., Job, D.: The Genetic Algorithm as a Discovery Engine: Strange Circuits and New Principles. In: Proceedings of the AISB Symposium on Creative Evolutionary Systems (CES 1999), Edinburgh, UK (1999)Google Scholar
  3. 3.
    Kalganova, T., Miller, J.: Evolving more efficient digital circuits by allowing circuit layout and multi-objective fitness. In: Proceedings of the First NASA/DoD Workshop on Evolvable Hardware, Los Alamitos, California, pp. 54–63 (1999)Google Scholar
  4. 4.
    Coello Coello, C.A., Christiansen, A.D., Aguirre, A.H.: Automated Design of Combinational Logic Circuits using Genetic Algorithms. In: Proc. of the Int. Conference on Artificial Neural Nets and Genetic Algorithms, pp. 335–338 (April 1997)Google Scholar
  5. 5.
    Coello Coello, C.A., Aguirre, A.H., Buckles, B.P.: Evolutionary Multiobjective Design of Combinational Logic Circuits. In: Proc. of the Second NASA/DoD Workshop on Evolvable Hardware, Los Alamitos, California, pp. 161–170 (July 2000)Google Scholar
  6. 6.
    Coello Coello, C.A., Christiansen, A.D., Aguirre, A.H.: Use of Evolutionary Techniques to Automate the Design of Combinational Circuits. International Journal of Smart Engineering System Design (2000)Google Scholar
  7. 7.
    Słowik, A., Białko, M.: Design and Optimization of Combinational Digital Circuits Using Modified Evolutionary Algorithm. In: Rutkowski, L., Siekmann, J.H., Tadeusiewicz, R., Zadeh, L.A. (eds.) ICAISC 2004. LNCS (LNAI), vol. 3070, pp. 468–473. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  8. 8.
    Slowik, A., Bialko, M.: Evolutionary Design and Optimization of Combinational Digital Circuits with Respect to Transistor Count. Bulletin of the Polish Academy of Sciences, Technical Sciences 54(4), 437–442 (2006)MATHGoogle Scholar
  9. 9.
    De Micheli, G.: Synthesis and Optimization of Digital Circuits. McGraw-Hill, New York (1994)Google Scholar
  10. 10.
    Saha, A.: Digital Principles and Logic Design. Jones & Bartlett Publishers (2007)Google Scholar
  11. 11.
    Schneier, B.: Applied Cryptography. Wiley, Chichester (1996)MATHGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2009

Authors and Affiliations

  • Adam Slowik
    • 1
  • Jacek M. Zurada
    • 2
  1. 1.Department of Electronics and Computer ScienceKoszalin University of TechnologyKoszalinPoland
  2. 2.Department of Electrical and Computer EngineeringUniversity of LouisvilleLouisvilleUSA

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