Ultra-Fast Downloading of Partial Bitstreams through Ethernet

  • Pierre Bomel
  • Jeremie Crenne
  • Linfeng Ye
  • Jean-Philippe Diguet
  • Guy Gogniat
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5455)


In this paper we present a partial bitstreams ultra-fast downloading process through a standard Ethernet network. These Virtex-based and partially reconfigurable systems use a specific data-link level protocol to communicate with remote bistreams servers. Targeted applications cover portable communicating low cost equipments, multi-standards software defined radio, automotive embedded electronics, mobile robotics or even spacecrafts where dynamic reconfiguration of FPGAs reduces the components count: hence the price, the weight, the power consumption, etc... These systems require a local network controller and a very small internal memory to support this specific protocol. Measures, based on real implementations, show that our systems can download partial bistreams with a speed twenty times faster (a sustained rate of 80 Mbits/s over Ethernet 100 Mbit/s) than best known solutions with memory requirements in the range of 10th of KB.


partial reconfiguration FPGA link layer bitstream server ultra-fast downloading Ethernet 


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  1. 1.
    Huebner, M., et al.: Real-time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration. In: Proc. of the 11th Reconfigurable Architectures Workshop (RAW/IPDPS 2004), Santa Fe, New Mexico, USA, April 26-30 (2004)Google Scholar
  2. 2.
    Haiyun, G., Shurong, C.: Partial Reconfiguration Bitstream Compression for Virtex FPGAs. In: Proc. of International Congress on Image and Signal Processing (CISP 2008), Sanya, Hainan, China, May 27-30 (2008)Google Scholar
  3. 3.
    Bomel, P., Gogniat, G., Diguet, J.-P.: A Networked, Lightweight and Partially Reconfigurable Platform. In: Woods, R., Compton, K., Bouganis, C., Diniz, P.C. (eds.) ARC 2008. LNCS, vol. 4943, pp. 318–323. Springer, Heidelberg (2008)CrossRefGoogle Scholar
  4. 4.
    Bomel, P., Gogniat, G., Diguet, J.-P., Crenne, J.: Bitstreams Repository Hierarchy for FPGA Partially Reconfigurable Systems. In: Proc. of 7th Intl. Symposium on Parallel and Distributed Computing (ISPDC 2008), Krakow, Poland, July 1-5 (2008)Google Scholar
  5. 5.
    Compton, K., Hauck, S.: Reconfigurable Computing: A Survey of Systems and Software. ACM Computing Surveys 34(2), 171–210 (2002)CrossRefGoogle Scholar
  6. 6.
    Walder, H., Platzner, M.: Online Scheduling for Block-partitioned Reconfigurable Devices. In: Proc. of Design, Automation and Test in Europe Conference and Exposition (DATE 2003), Munich, Germany, March 3-7 2003. IEEE Computer Society, Los Alamitos (2003)Google Scholar
  7. 7.
    Xilinx XAPP290. Two Flows for Partial Reconfiguration: Module Based or Difference Based (September 2004)Google Scholar
  8. 8.
    Blodget, B., McMillan, S., Lysaght, P.: A lightweight approach for embedded reconfiguration of fpgas. In: Proc. of Design, Automation and Test in Europe Conference and Exposition (DATE 2003), Munich, Germany, March 3-7, 2003. IEEE Computer Society, Los Alamitos (2003)Google Scholar
  9. 9.
    Claus, C., Zeppenfeld, J., Muller, F., Stechele, W.: Using Partial-Run-Time Reconfigurable Hardware to accelerate Video Processing in Driver Assistance System. In: Proc. of Design, Automation and Test in Europe Conference and Exposition (DATE 2007), Nice, France, April 20-24 (2007)Google Scholar
  10. 10.
    Xilinx, XAPP433. Web Server design using MicroBlaze Soft Processor (October 2006)Google Scholar
  11. 11.
    Adam Dunkels. lwIP. Computer and Networks Architectures (CNA), Swedish Institute of Computer Science, http://www.sics.se/~adam/lwip/
  12. 12.
    Lagger, A., Upegui, A., Sanchez, E.: Self-Reconfigurable Pervasive Platform For Cryptographic Application. In: Proc. of the 16th Intl. Conference on Field Programmable Logic and Applications (FPL 2006), Madrid, SPAIN, August 28-30 (2006)Google Scholar
  13. 13.
    Williams, J., Bergmann, N.: Embedded Linux as a platform for dynamically self-reconfiguring systems-on-chip. In: Proc. of the Intl. Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA 2004), Las Vegas, Nevada, USA, June 21-24 (2004)Google Scholar
  14. 14.
    Huebner, M., Becker, T., Becker, J.: Real-Time LUT-based Network Topologies for Dynamic and Partial FPGA Self-Reconfiguration. In: Proc. of the 17th Symposium on Integrated Circuits and Systems design (SBCCI 2004), Ipojuca, Brazil, September 7-11 (2004)Google Scholar
  15. 15.
    Bobda, C., Majer, M., Ahmadinia, A., Haller, T., Linarth, A., Teich, J.: The Erlangen Slot Machine: Increasing Flexibility in FPGA-Based Reconfigurable Platforms. Journal of VLSI Signal Processing Systems 47(1), 15–31 (2007)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2009

Authors and Affiliations

  • Pierre Bomel
    • 1
  • Jeremie Crenne
    • 1
  • Linfeng Ye
    • 1
  • Jean-Philippe Diguet
    • 1
  • Guy Gogniat
    • 1
  1. 1.Lab-STICCUniversité de Bretagne Sud, UEB, CNRS UMRLorientFrance

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