Towards Novel Approaches in Design Automation for FPGA Power Optimization

  • Juanjo Noguera
  • Robert Esser
  • Katarina Paulsson
  • Michael Hübner
  • Jürgen Becker
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5349)


The exploitation of reconfigurable architectures is currently increasing for high-performance applications e.g. signal processing systems. Until now however, general purpose processors are typically applied for lowpower applications partly due to the un-optimized design process of FPGA systems. Currently, the increasing requirements even on low-power applications force the investigation of alternative architectures such as FPGAs to enable higher flexibility for such applications. This paper presents a multi-level overview of power optimization for FPGA-based systems. Several novel design considerations for power reduction are described and discussed as well as the achieved results. The main objective of the presented work is to enable the flexibility of reconfigurable architectures even for low-power applications.


Power Consumption Field Programmable Gate Array Clock Frequency Leakage Power Dynamic Power Consumption 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Paulsson, K., Hübner, M., Becker, J.: On-Line Optimization of FPGA Power- Dissipation by Exploiting Run-time Adaption of Communication Primitives. In: SBCCI 2006, Brazil (2006)Google Scholar
  2. 2.
    Paulsson, K., Huebner, M., Becker, J.: Cost - and Power Optimized FPGA Based System Integration: Methodologies and Integration of a Low-Power Capacity- Based Measurement Application on Xilinx FPGA. In: DATE 2008, Munich, Germany (2008)Google Scholar
  3. 3.
    IBM; On-Chip Peripheral Bus, Architecture Specifications (2001)Google Scholar
  4. 4.
    Shang, L., Kaviani, S.A.S., Bathala, K.: Dynamic Power Consumption in Virtex II FPGA Family. In: Proc. of the 2002 ACM/SIGDA 10th Int. Symp. on Field- Programmable Gate Arrays (2002)Google Scholar
  5. 5.
    Ullmann, M., Hübner, M., Grimm, B., Becker, J.: An FPGA Run-Time System for Dynamical On-Demand Reconfiguration. In: Proc. of the 11th Reconfigurable Architectures Workshop (RAW/IPDPS) (April 2004)Google Scholar
  6. 6.
    Paulsson, K., Auer, G., Dreschmann, M., Hübner, M., Becker, J.: Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self- Reconfiguration on Xilinx Spartan III FPGAs. In: FPL 2007, Amsterdam, Netherlands (2007)Google Scholar
  7. 7.
    Xilinx; Spartan III FPGA Family, DS099 (April 2006)Google Scholar
  8. 8.
    Xilinx; MicroBlaze Processor Reference Guide, UG086 (v6.0) (June 2006)Google Scholar
  9. 9.
    Gupta, S., Anderson, J.: Optimizing FPGA Power with ISE Design Tools. Xcell Journal, Second Quarter (2007)Google Scholar
  10. 10.
    Degalahal, V., Tuan, T.: Methodology for High Level Estimation of FPGA Power Consumption. In: Proc. of ASP-DAC 2005 Conference, Shanghai (January 2005)Google Scholar
  11. 11.
    Attig, M., Brebner, G.: Systematic Characterization of Programmable Packet Processing Pipelines. In: IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2006, Napa, CA, USA (2006)Google Scholar
  12. 12.
    Wilton, S., Ang, S., Luk, W.: The Impact of Pipelining on Energy per Operation in Field Programmable Gate Arrays. In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL 2004) (2004)Google Scholar
  13. 13.
    Stitt, G., Grattan, B., Villarreal, J., Vahid, F.: Using on-chip configurable logic to reduce embedded system software energy. In: Proceedings of the IEEE Symposium on Field Programmable Custom Computing Machines (FCCM 2002) (2002)Google Scholar
  14. 14.
    Noguera, J., Badia, R.: System-level Power-Performance Trade-Offs for Reconfigurable Computing. IEEE Transactions on Very Large Scale Integration Systems, Special issue on Hardware/Software co-design (2006)Google Scholar
  15. 15.
    Becker, Hübner, Ullmann: Power Estimation and Power Mesurement of Xilinx Virtex FPGAs: Trade-offs and Limitations. In: SBCCI 2003 (2003)Google Scholar
  16. 16.
    Cong, J., Chen, D., He, L., Li, F., Lin, Y.: Architecture and Synthesis for Power Efficient FPGAs. In: 2004 IEEE Electronic Design Process Symposium (EDPS), Monterey, California (April 2004)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2009

Authors and Affiliations

  • Juanjo Noguera
    • 1
  • Robert Esser
    • 1
  • Katarina Paulsson
    • 2
  • Michael Hübner
    • 2
  • Jürgen Becker
    • 2
  1. 1.Xilinx Research LabsDublinIreland
  2. 2.Institute for Information TechnologiesUniversität Karlsruhe (TH)KarlsruheGermany

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