Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs

  • Bahman Kheradmand Boroujeni
  • Christian Piguet
  • Yusuf Leblebici
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5349)


In this work we present a new static circuit topology for sub-threshold (sub-VT) digital design. Proposed topology is derived from SCMOS but modifications are done to introduce new adjustable parameters to provide about 4X more control on the delay and active-mode leakage of gates. Proposed gates have full-swing input and output signaling but when the internal NMOS/PMOS transistors are off, they have negative Vgs/Vsg bias, respectively. By controlling the amount of these reverse biases, we can compensate process and temperature variations. Proposed method can be applied to any device or technology node and has 20% area and delay overheads.


Sub-VToperation process variations variation compensation logic style active-mode leakage 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2009

Authors and Affiliations

  • Bahman Kheradmand Boroujeni
    • 1
    • 2
  • Christian Piguet
    • 1
  • Yusuf Leblebici
    • 2
  1. 1.Centre Suisse d’Electronique et de Microtechnique (CSEM)NeuchâtelSwitzerland
  2. 2.Ecole Polytechnique Fédérale de Lausanne (EPFL)LausanneSwitzerland

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