Investigating Cache Parameters of x86 Family Processors

  • Vlastimil Babka
  • Petr Tůma
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5419)

Abstract

The excellent performance of the contemporary x86 processors is partially due to the complexity of their memory architecture, which therefore plays a role in performance engineering efforts. Unfortunately, the detailed parameters of the memory architecture are often not easily available, which makes it difficult to design experiments and evaluate results when the memory architecture is involved. To remedy this lack of information, we present experiments that investigate detailed parameters of the memory architecture, focusing on such information that is typically not available elsewhere.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Intel Corporation: Intel 64 and IA-32 Architectures Software Developer Manual, Volume 3: System Programming, Order Nr. 253668-027 and 253669-027 (July 2008)Google Scholar
  2. 2.
    Advanced Micro Devices, Inc.: AMD64 Architecture Programmer’s Manual Volume 2: System Programming, Publication Number 24593, Revision 3.14. (September 2007)Google Scholar
  3. 3.
    Drepper, U.: What every programmer should know about memory (2007), http://people.redhat.com/drepper/cpumemory.pdf
  4. 4.
    PAPI: Performance application programming interface, http://icl.cs.utk.edu/papi
  5. 5.
  6. 6.
    Advanced Micro Devices, Inc.: AMD BIOS and Kernel Developer’s Guide For AMD Family 10h Processors, Publication Number 31116, Revision 3.06 (March 2008)Google Scholar
  7. 7.
    Babka, V., Bulej, L., Děcký, M., Kraft, J., Libič, P., Marek, L., Seceleanu, C., Tůma, P.: Resource usage modeling, Q-ImPrESS deliverable 3.3 (September 2008), http://www.q-impress.eu
  8. 8.
    Intel Corporation: Intel 64 and IA-32 Architectures Application Note: TLBs, Paging-Structure Caches, and Their Invalidation, Order Nr. 317080-002 (April 2008)Google Scholar
  9. 9.
    Advanced Micro Devices, Inc.: AMD Software Optimization Guide for AMD Family 10h Processors, Publication Number 40546, Revision 3.06 (April 2008)Google Scholar
  10. 10.
    Yotov, K., Pingali, K., Stodghill, P.: Automatic measurement of memory hierarchy parameters. In: Proceedings of the 2005 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, pp. 181–192. ACM, New York (2005)CrossRefGoogle Scholar
  11. 11.
    Intel Corporation: Intel 64 and IA-32 Architectures Optimization Reference Manual, Order Nr. 248966-016 (November 2007)Google Scholar
  12. 12.
    R: The R Project for Statistical Computing, http://www.r-project.org/
  13. 13.
    Kessler, R.E., Hill, M.D.: Page placement algorithms for large real-indexed caches. ACM Trans. Comput. Syst. 10(4), 338–359 (1992)CrossRefGoogle Scholar
  14. 14.
    Yotov, K., Jackson, S., Steele, T., Pingali, K.K., Stodghill, P.: Automatic measurement of instruction cache capacity. In: Ayguadé, E., Baumgartner, G., Ramanujam, J., Sadayappan, P. (eds.) LCPC 2005. LNCS, vol. 4339, pp. 230–243. Springer, Heidelberg (2006)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2009

Authors and Affiliations

  • Vlastimil Babka
    • 1
  • Petr Tůma
    • 1
  1. 1.Department of Software Engineering Faculty of Mathematics and PhysicsCharles UniversityPrague 1Czech Republic

Personalised recommendations