A High Performance H.264 Deblocking Filter

  • Vagner Rosa
  • Altamiro Susin
  • Sergio Bampi
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5414)

Abstract

Although the H.264 Deblocking Filter process is a relatively small piece of code in a software implementation, profile results shows it cost about a third of the total CPU time in the decoder. This work presents a high performance architecture for implementing a H.264 Deblocking Filter IP that can be used either in the decoder or in the encoder as a hardware accelerator for a processor or embedded in a full-hardware codec. A developed IP using the proposed architecture support multiple high definition processing flows in real-time.

Keywords

Clock Cycle Horizontal Edge Input Buffer Pipeline Architecture Boundary Strength 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2009

Authors and Affiliations

  • Vagner Rosa
    • 1
  • Altamiro Susin
    • 1
  • Sergio Bampi
    • 1
  1. 1.Informatics InstituteFederal University of Rio Grande do SulBairro Agronomia - Porto AlegreBrasil

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