On the Importance of the Number of Fanouts to Prevent the Glitches in DPA-Resistant Devices
During the last years several logic styles have been proposed to counteract power analysis attacks. This article starts with a brief review of four different logic styles namely RSL, MDLP, DRSL, and TDPL. This discussion continues to examine the effect of the number of fanouts in power consumption of a CMOS inverter. Moreover, it is shown that insertion of delay elements in typical CMOS circuits is not adequate to prevent the glitches and information leakage unless the fanouts of input signals are balanced. Whereas enable signals have to be classified according to the depth of combinational circuits implemented using pre-charge logic styles, we show that the number of fanouts of enable signals (which is equal to the number of gates in each depth) is a significant factor in determining the interval between arrival time of the consecutive enable signals.
KeywordsDPA Glitches Delay Elements Fanouts Dual-Rail Logics Pre-Charge Logics
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- 10.Suzuki, D., Saeki, M., Ichikawa, T.: Random Switching Logic: A Countermeasure against DPA based on Transition Probability. Cryptology ePrint Archive, Report 2004/346 (2004), http://eprint.iacr.org/
- 11.Tiri, K., Akmal, M., Verbauwhede, I.: A Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand Differential Power Analysis on Smart Cards. In: European Solid-State Circuits Confer., pp. 403–406 (2002)Google Scholar
- 12.Tiri, K., Verbauwhede, I.: A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation. In: DATE 2004, pp. 246–251. IEEE Computer Society, Los Alamitos (2004)Google Scholar
- 13.Weste, N.H.E., Eshraghian, K.: Principles of CMOS VLSI Design – A Systems Perspective, 2nd edn. Addison-Wesley, Reading (1993)Google Scholar