On the Importance of the Number of Fanouts to Prevent the Glitches in DPA-Resistant Devices

  • Amir Moradi
  • Mahmoud Salmasizadeh
  • Mohammad Taghi Manzuri Shalmani
Part of the Communications in Computer and Information Science book series (CCIS, volume 6)

Abstract

During the last years several logic styles have been proposed to counteract power analysis attacks. This article starts with a brief review of four different logic styles namely RSL, MDLP, DRSL, and TDPL. This discussion continues to examine the effect of the number of fanouts in power consumption of a CMOS inverter. Moreover, it is shown that insertion of delay elements in typical CMOS circuits is not adequate to prevent the glitches and information leakage unless the fanouts of input signals are balanced. Whereas enable signals have to be classified according to the depth of combinational circuits implemented using pre-charge logic styles, we show that the number of fanouts of enable signals (which is equal to the number of gates in each depth) is a significant factor in determining the interval between arrival time of the consecutive enable signals.

Keywords

DPA Glitches Delay Elements Fanouts Dual-Rail Logics Pre-Charge Logics 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Bucci, M., Giancane, L., Luzzi, R., Trifiletti, A.: Three-Phase Dual-Rail Pre-charge Logic. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol. 4249, pp. 232–241. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  2. 2.
    Chen, Z., Zhou, Y.: Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol. 4249, pp. 242–254. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  3. 3.
    Fischer, W., Gammel, B.M.: Masking at Gate Level in the Presence of Glitches. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 187–200. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  4. 4.
    Kocher, P.C., Jaffe, J., Jun, B.: Differential Power Analysis. In: Wiener, M. (ed.) CRYPTO 1999. LNCS, vol. 1666, pp. 388–397. Springer, Heidelberg (1999)CrossRefGoogle Scholar
  5. 5.
    Mangard, S., Pramstaller, N., Oswald, E.: Successfully Attacking Masked AES Hardware Implementations. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 157–171. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  6. 6.
    Mangard, S., Schramm, K.: Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol. 4249, pp. 76–90. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  7. 7.
    Oswald, E., Mangard, S., Pramstaller, N., Rijmen, V.: A Side-Channel Analysis Resistant Description of the AES S-box. In: Gilbert, H., Handschuh, H. (eds.) FSE 2005. LNCS, vol. 3557, pp. 413–423. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  8. 8.
    Popp, T., Mangard, S.: Masked Dual-Rail Pre-Charge Logic: DPA Resistance without Routing Constraints. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 172–186. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  9. 9.
    Suzuki, D., Saeki, M.: Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol. 4249, pp. 255–269. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  10. 10.
    Suzuki, D., Saeki, M., Ichikawa, T.: Random Switching Logic: A Countermeasure against DPA based on Transition Probability. Cryptology ePrint Archive, Report 2004/346 (2004), http://eprint.iacr.org/
  11. 11.
    Tiri, K., Akmal, M., Verbauwhede, I.: A Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand Differential Power Analysis on Smart Cards. In: European Solid-State Circuits Confer., pp. 403–406 (2002)Google Scholar
  12. 12.
    Tiri, K., Verbauwhede, I.: A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation. In: DATE 2004, pp. 246–251. IEEE Computer Society, Los Alamitos (2004)Google Scholar
  13. 13.
    Weste, N.H.E., Eshraghian, K.: Principles of CMOS VLSI Design – A Systems Perspective, 2nd edn. Addison-Wesley, Reading (1993)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Amir Moradi
    • 1
  • Mahmoud Salmasizadeh
    • 2
  • Mohammad Taghi Manzuri Shalmani
    • 1
  1. 1.Department of Computer EngineeringSharif University of TechnologyTehranIran
  2. 2.Electronic Research CenterSharif University of TechnologyTehranIran

Personalised recommendations