Timing Validation of Automotive Software

  • Daniel Kästner
  • Reinhard Wilhelm
  • Reinhold Heckmann
  • Marc Schlickling
  • Markus Pister
  • Marek Jersak
  • Kai Richter
  • Christian Ferdinand
Part of the Communications in Computer and Information Science book series (CCIS, volume 17)

Abstract

Embedded hard real-time systems need reliable guarantees for the satisfaction of their timing constraints. During the last years sophisticated analysis tools for timing analysis at the code-level, controller-level and networked system-level have been developed. This trend is exemplified by two tools: AbsInt’s timing analyzer aiT, and and Symtavision’s SymTA/S. aiT determines safe upper bounds for the execution times (WCETs) of non-interrupted tasks. SymTA/S computes the worst-case response times (WCRTs) of an entire system from the task WCETs and from information about possible interrupts and their priorities. A seamless integration between both tools provides for a holistic approach to timing validation: starting from a system model, a designer can perform timing budgeting, performance optimization and timing verification, thus covering both the code and the system aspects. However, the precision of the results and the efficiency of the analysis methods are highly dependent on the predictability of the execution platform. Especially on multi-core architectures this aspect becomes of critical importance. This paper describes an industry-strength tool flow for timing validation, and discusses prerequisites at the hardware level for ascertaining high analysis precision.

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References

  1. 1.
    Al-Zoubi, H., Milenkovic, A., Milenkovic, M.: Performance evaluation of cache replacement policies for the SPEC CPU2000 benchmark suite. In: ACM-SE 42: Proceedings of the 42nd Annual Southeast Regional Conference, pp. 267–272. ACM Press, New York (2004)CrossRefGoogle Scholar
  2. 2.
    T. AUTOSAR Development Partnership. Automotive Open System Architecture (AUTOSAR) (2003), http://www.autosar.org
  3. 3.
    Berg, C.: PLRU cache domino effects. In: Proceedings of 6th International Workshop on Worst-Case Execution Time (WCET) Analysis (July 2006)Google Scholar
  4. 4.
    Bernat, G., Colin, A., Petters, S.M.: WCET analysis of probabilistic hard real-time systems. In: RTSS 2002: Proceedings of the 23rd IEEE Real-Time Systems Symposium (RTSS 2002), Washington, DC, USA, p. 279. IEEE Computer Society, Los Alamitos (2002)CrossRefGoogle Scholar
  5. 5.
    Deverge, J.-F., Puaut, I.: Safe measurement-based WCET estimation. In: Wilhelm, R. (ed.) 5th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis, Dagstuhl, Germany, Internationales Begegnungs- und Forschungszentrum für Informatik (IBFI), Schloss Dagstuhl, Germany (2005)Google Scholar
  6. 6.
    Engblom, J.: Processor Pipelines and Static Worst-Case Execution Time Analysis. PhD thesis, Dept. of Information Technology, Uppsala University (2002)Google Scholar
  7. 7.
  8. 8.
  9. 9.
    Ferdinand, C., Heckmann, R., Langenbach, M., Martin, F., Schmidt, M., Theiling, H., Thesing, S., Wilhelm, R.: Reliable and precise WCET determination for a real-life processor. In: Henzinger, T.A., Kirsch, C.M. (eds.) EMSOFT 2001. LNCS, vol. 2211, pp. 469–485. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  10. 10.
    Ferdinand, C., Martin, F., Cullmann, C., Schlickling, M., Stein, I., Thesing, S., Heckmann, R.: New developments in WCET analysis. In: Reps, T., Sagiv, M., Bauer, J. (eds.) Wilhelm Festschrift. LNCS, vol. 4444, pp. 12–52. Springer, Heidelberg (2007)CrossRefGoogle Scholar
  11. 11.
    Ferdinand, C., Wilhelm, R.: Efficient and precise cache behavior prediction for real-time systems. Real-Time Systems 17(2-3), 131–181 (1999)CrossRefGoogle Scholar
  12. 12.
    Freescale Semiconductor, Inc. PowerPC Microprocessor Family: The Bus Interface for 32-Bit Microprocessors, Rev. 0.1 (2004)Google Scholar
  13. 13.
    Heckmann, R., Langenbach, M., Thesing, S., Wilhelm, R.: The influence of processor architecture on the design and the results of WCET tools. IEEE Proceedings on Real-Time Systems 91(7), 1038–1054 (2003)Google Scholar
  14. 14.
    Henia, R., Hamann, A., Jersak, M., Racu, R., Richter, K., Ernst, R.: System level performance analysis – the SymTA/S approach. IEEE Proceedings on Computers and Digital Techniques 152(2) (March 2005)Google Scholar
  15. 15.
    Lee, C.-G., Hahn, J., Min, S.L., Ha, R., Hong, S., Park, C.Y., Lee, M., Kim, C.S.: Analysis of cache-related preemption delay in fixed-priority preemptive scheduling. In: RTSS 1996: Proceedings of the 17th IEEE Real-Time Systems Symposium (RTSS 1996), Washington, DC, USA, p. 264. IEEE Computer Society, Los Alamitos (1996)Google Scholar
  16. 16.
    Li, Y.-T.S., Malik, S.: Performance Analysis of Embedded Software Using Implicit Path Enumeration. In: Proceedings of the 32nd ACM/IEEE Design Automation Conference (1995)Google Scholar
  17. 17.
    Lundqvist, T., Stenström, P.: Timing anomalies in dynamically scheduled microprocessors. In: Proceedings of the 20th IEEE Real-Time Systems Symposium (RTSS 1999), pp. 12–21 (December 1999)Google Scholar
  18. 18.
    Petters, S.M.: Worst Case Execution Time Estimation for Advanced Processor Architectures. PhD thesis, Technische Universität München, Munich, Germany (September 2002)Google Scholar
  19. 19.
    Petters, S.M., Zadarnowski, P., Heiser, G.: Measurements or static analysis or both? In: Rochange, C. (ed.) WCET (2007)Google Scholar
  20. 20.
    Puaut, I., Decotigny, D.: Low-complexity algorithms for static cache locking in multitasking hard real-time systems. In: RTSS 2002: Proceedings of the 23rd IEEE Real-Time Systems Symposium (RTSS 2002), Washington, DC, USA, p. 114. IEEE Computer Society, Los Alamitos (2002)CrossRefGoogle Scholar
  21. 21.
    Reineke, J., Grund, D.: Sensitivity of cache replacement policies. Reports of SFB/TR 14 AVACS 36, SFB/TR 14 AVACS (March 2008)ISSN: 1860-9821, http://www.avacs.org
  22. 22.
    Reineke, J., Grund, D., Berg, C., Wilhelm, R.: Timing predictability of cache replacement policies. Real-Time Systems 37(2), 99–122 (2007)CrossRefMATHGoogle Scholar
  23. 23.
    Reineke, J., Wachter, B., Thesing, S., Wilhelm, R., Polian, I., Eisinger, J., Becker, B.: A definition and classification of timing anomalies. In: Proceedings of 6th International Workshop on Worst-Case Execution Time (WCET) Analysis (July 2006)Google Scholar
  24. 24.
    Schliecker, S., Ivers, M., Ernst, R.: Integrated analysis of communicating tasks in MPSoCs. In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, pp. 288–293. ACM Press, New York (2006)Google Scholar
  25. 25.
    Schneider, J.: Combined Schedulability and WCET Analysis for Real-Time Operating Systems. PhD thesis, Saarland University (2003)Google Scholar
  26. 26.
    Schneider, J., Ferdinand, C.: Pipeline Behavior Prediction for Superscalar Processors by Abstract Interpretation. In: Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems, vol. 34, pp. 35–44 (May 1999)Google Scholar
  27. 27.
    Theiling, H.: Extracting Safe and Precise Control Flow from Binaries. In: Proceedings of the 7th Conference on Real-Time Computing Systems and Applications, Cheju Island, South Korea (2000)Google Scholar
  28. 28.
    Theiling, H., Ferdinand, C.: Combining abstract interpretation and ILP for microarchitecture modelling and program path analysis. In: Proceedings of the 19th IEEE Real-Time Systems Symposium, Madrid, Spain, pp. 144–153 (December 1998)Google Scholar
  29. 29.
    Thesing, S.: Safe and Precise WCET Determinations by Abstract Interpretation of Pipeline Models. PhD thesis, Saarland University (2004)Google Scholar
  30. 30.
    Thesing, S., Souyris, J., Heckmann, R., Randimbivololona, F., Langenbach, M., Wilhelm, R., Ferdinand, C.: An abstract interpretation-based timing validation of hard real-time avionics software systems. In: Proceedings of the 2003 International Conference on Dependable Systems and Networks (DSN 2003), June 2003, pp. 625–632. IEEE Computer Society, Los Alamitos (2003)CrossRefGoogle Scholar
  31. 31.
    Vera, X., Lisper, B., Xue, J.: Data cache locking for higher program predictability. SIGMETRICS Perform. Eval. Rev. 31(1), 272–282 (2003)CrossRefGoogle Scholar
  32. 32.
    Wenzel, I.: Measurement-Based Timing Analysis of Superscalar Processors. PhD thesis, Technische Universität Wien, Institut für Technische Informatik, Treitlstr. 3/3/182-1, 1040 Vienna, Austria (2006)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Daniel Kästner
    • 1
  • Reinhard Wilhelm
    • 2
  • Reinhold Heckmann
    • 1
  • Marc Schlickling
    • 1
    • 2
  • Markus Pister
    • 1
    • 2
  • Marek Jersak
    • 3
  • Kai Richter
    • 3
  • Christian Ferdinand
    • 1
  1. 1.AbsInt GmbHSaarbrückenGermany
  2. 2.Saarland UniversitySaarbrückenGermany
  3. 3.Symtavision GmbHBraunschweigGermany

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