Proposal for LDPC Code Design System Using Multi-Objective Optimization and FPGA-Based Emulation
The paper proposes a low density parity check (LDPC) code design system to facilitate the design of communication systems using LDPC codes for error correction. The proposed LDPC code design system has three advantages (utilization of MOGA to search codes, speed enhancement achieved through parallelization and FPGAs, and employment of more precise simulation models) and solves problems encountered when LDPC codes are used in practical applications. Preliminary evaluation results for the proposed system are presented, which demonstrate that the system can function successfully.
Keywordserror-correcting code LDPC multi-objective optimization MOGA communication channel model ISI FPGA emulation parallelization MPI PC cluster
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- 1.Gallager, R.: Low-Density Parity-Check Codes. MIT Press, Cambridge (1963)Google Scholar
- 3.Lin, S., Costello, J.D.: Error Control Coding, 2nd edn. PEARSON Prentice Hall (2004)Google Scholar
- 4.Shannon, C.E., Weaver, W.: The Mathematical Theory of Communication. University of Illinois Press (1963)Google Scholar
- 5.Seki, K., Itabashi, T., Higuchi, T., Kasai, Y., Takahashi, E.: Performance evaluation of low latency LDPC code. Technical report, IEEE P802.3an July 2004 Plenary (2004)Google Scholar
- 6.Coello, C.C.: A comprehensible survey of evolutionary -based multi-objective optimization techniques. Knowledge and Information Systems 1(3), 269–308 (1999)Google Scholar
- 8.Cantú-Paz, E.: A summary of research on parallel genetic algorithms. IlliGAL Report 97003, University of Illinois (1997)Google Scholar
- 9.Forum, M.P.I.: MPI-2: Extensions to the message-passing interface (2003), http://www.mpi-forum.org
- 10.Culler, D.E., Singh, J.P., Gupta, A.: Parallel Computer Archtecture, A Hardware/Software Approach. Morgan Kaufmann, San Francisco (1999)Google Scholar