Verifying Compiler Based Refinement of BluespecTM Specifications Using the SPIN Model Checker

  • Gaurav Singh
  • Sandeep K. Shukla
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5156)

Abstract

The underlying model of computation for PROMELA is based on interacting processes with asynchronous communication, and hence SPIN has been mainly used as a verification engine for concurrent software systems. On the other hand, hardware verification has mostly focused on clock synchronous register-transfer level (RTL) models. As a result, verification tools such as SMV which are based on synchronous state machine models have been used more frequently for hardware verification. However, as levels of abstractions are being raised in hardware design and as high-level synthesis is being promoted for synthesizing RTL, hardware design verification problems are changing in nature. In this paper, we consider a specific high-level hardware description langauge, namely, Bluespec System Verilog (BSV). The programming model of BSV is based on concurrent guarded actions, which we also call as Concurrent Action Oriented Specification (CAOS). High-level synthesis from BSV models has been shown to produce efficient RTL designs. Given the industry traction of BSV-based high-level synthesis and associated design flow, we consider the following formal verification problems: (i) Given a BSV specification \({\cal S}\) of a hardware design, does it satisfy certain temporal properties? (ii) Given a BSV specification \({\cal S}\), and an implementation R synthesized from \({\cal S}\) using a BSV-based synthesis tool, does R conform to the behaviors specified by \({\cal S}\); that is, is R a refinement of \({\cal S}\)? (iii) Given a different implementation R synthesized from \({\cal S}\) using some other BSV-based synthesis tool, is R a refinement of R as well? In this paper, we show how SPIN Model Checker can be used to solve these three problems related to the verification of BSV-based designs. Using a sample design, we illustrate how our approach can be used for verifying whether the designer intent in the BSV specification is accurately matched by its synthesized hardware implementation.

Keywords

Formal Verification Hardware Designs Bluespec System Verilog (BSV) SPIN Model Checker 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Holzmann, G.J.: The SPIN Model Checker. Addison Wesley, Reading (2004)Google Scholar
  2. 2.
    Holzmann, G.J.: The model checker SPIN. Software Engineering 23(5), 279–295 (1997)MathSciNetCrossRefGoogle Scholar
  3. 3.
  4. 4.
    Raghunathan, A., Jha, N.K., Dey, S.: High-Level Power Analysis And Optimization. Kluwer Academic Publishers, Dordrecht (1998)MATHGoogle Scholar
  5. 5.
    Singh, G., Shukla, S.K.: Low-Power Hardware Synthesis from TRS-based Specifications. In: International Conference on Formal Methods and Models for Codesign (MEMOCODE 2006) (2006)Google Scholar
  6. 6.
    Singh, G., Schwartz, J.B., Ahuja, S., Shukla, S.K.: Techniques for Power-aware Hardware Synthesis from Concurrent Action Oriented Specifications. Journal of Low Power Electronics (JOLPE) 3(2), 156–166 (2007)CrossRefGoogle Scholar
  7. 7.
    Hoe, J.C.: Arvind: Hardware Synthesis from Term Rewriting Systems. In: Proceeding of VLSI 1999, Lisbon, Portugal (December 1999)Google Scholar
  8. 8.
    Arvind, N.R., Rosenband, D., Dave, N.: High-level synthesis: An Essential Ingredient for Designing Complex ASICs. In: Proceedings of the International Conference on Computer Aided Design (ICCAD 2004), November 2004, pp. 775–782 (2004)Google Scholar
  9. 9.
    Singh, G., Shukla, S.K.: Model Checking Bluespec Specified Hardware Designs. In: Microprocessor Test and Verification (MTV 2007) (2007)Google Scholar
  10. 10.
    Lamport, L.: The temporal logic of actions. ACM Transactions on Programming Languages and Systems 16(3), 872–923 (1994)CrossRefGoogle Scholar
  11. 11.
    Singh, G., Shukla, S.K.: Verifying Compiler Based Refinement of Bluespec Specifications using the SPIN Model Checker. Technical report 2008-03, Virginia Tech, FERMAT Lab, Blacksburg, VA (April 2008), http://fermat.ece.vt.edu/Publications/pubs/techrep/techrep0803.pdf

Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Gaurav Singh
    • 1
  • Sandeep K. Shukla
    • 1
  1. 1.FERMAT Lab, Deptt of Electrical and Computer EngineeringVirginia TechBlacksburgUSA

Personalised recommendations