A Very Compact Hardware Implementation of the MISTY1 Block Cipher

  • Dai Yamamoto
  • Jun Yajima
  • Kouichi Itoh
Conference paper

DOI: 10.1007/978-3-540-85053-3_20

Part of the Lecture Notes in Computer Science book series (LNCS, volume 5154)
Cite this paper as:
Yamamoto D., Yajima J., Itoh K. (2008) A Very Compact Hardware Implementation of the MISTY1 Block Cipher. In: Oswald E., Rohatgi P. (eds) Cryptographic Hardware and Embedded Systems – CHES 2008. CHES 2008. Lecture Notes in Computer Science, vol 5154. Springer, Berlin, Heidelberg

Abstract

This paper proposes compact hardware (H/W) implementation for the MISTY1 block cipher, which is an ISO/IEC18033 standard encryption algorithm. In designing the compact H/W, we focused on optimizing the implementation of FO/FI functions, which are the main components of MISTY1. For this optimization, we propose two new methods; reducing temporary registers for the FO function, and shortening the critical path for the FI function. According to our logic synthesis on a 0.18-μm CMOS standard cell library based on our proposed method, the gate size is 3.95 Kgates, which is the smallest as far as we know.

Keywords

Block cipher MISTY1 Hardware ASIC Compact Implementation 

Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Dai Yamamoto
    • 1
  • Jun Yajima
    • 1
  • Kouichi Itoh
    • 1
  1. 1.FUJITSU LABORATORIES LTD.KawasakiJapan

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