A New Bit-Serial Architecture for Field Multiplication Using Polynomial Bases

  • Arash Reyhani-Masoleh
Conference paper

DOI: 10.1007/978-3-540-85053-3_19

Part of the Lecture Notes in Computer Science book series (LNCS, volume 5154)
Cite this paper as:
Reyhani-Masoleh A. (2008) A New Bit-Serial Architecture for Field Multiplication Using Polynomial Bases. In: Oswald E., Rohatgi P. (eds) Cryptographic Hardware and Embedded Systems – CHES 2008. CHES 2008. Lecture Notes in Computer Science, vol 5154. Springer, Berlin, Heidelberg

Abstract

Multiplication is the main finite field arithmetic operation in elliptic curve cryptography and its bit-serial hardware implementation is attractive in resource constrained environments such as smart cards, where the chip area is limited. In this paper, a new serial-output bit-serial multiplier using polynomial bases over binary extension fields is proposed. It generates a bit of the multiplication in each clock cycle with the latency of one cycle. To the best of our knowledge, this is the first time that such a serial-output bit-serial multiplier architecture using polynomial bases for general irreducible polynomials is proposed.

Keywords

Finite or Galois field Mastrovito multiplier polynomial basis bit-serial multiplier 

Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Arash Reyhani-Masoleh
    • 1
  1. 1.Department of Electrical and Computer EngineeringThe University of Western OntarioLondonCanada

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