Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors

  • P. Bernardi
  • K. Christou
  • M. Grosso
  • M. K. Michael
  • E. Sánchez
  • M. Sonza Reorda
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4974)

Abstract

This paper presents an innovative approach for the generation of test programs detecting path-delay faults in microprocessors. The proposed method takes advantage of the multiobjective implementation of a previously devised evolutionary algorithm and exploits both gate- and RT-level descriptions of the processor: the former is used to build Binary Decision Diagrams (BDDs) for deriving fault excitation conditions; the latter is used for the automatic generation of test programs able to excite and propagate fault effects, based on a fast RTL simulation. Experiments on an 8-bit microcontroller show that the proposed method is able to generate suitable test programs more efficiently compared to existing approaches.

Keywords

MOEA path-delay testing microprocessor BDD 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Mak, T.M., et al.: New challenges in delay testing of nanometer, multigigahertz designs. IEEE Design & Test of Computers 21(3), 241–248 (2004)CrossRefGoogle Scholar
  2. 2.
    Lin, C.J., Reddy, S.M.: On Delay Fault Testing in Logic Circuits. IEEE Trans. on CAD 6(5), 694–703 (1987)Google Scholar
  3. 3.
    Chakraborty, T.J., et al.: Delay fault models and test generation for random logic sequential circuits. In: ACM/IEEE Design Automation Conference, pp. 165–172 (1992)Google Scholar
  4. 4.
    Kim, K.S., Mitra, S., Ryan, P.G.: Delay defect characteristics and testing strategies. IEEE Design & Test of Computers 20(5), 8–16 (2003)CrossRefGoogle Scholar
  5. 5.
    Krstic, A., Cheng, K.-T.: Delay Fault Testing for VLSI circuits. Kluwer Academic Publishers, Dordrecht (1998)Google Scholar
  6. 6.
    Fuchs, K., Pabst, M., Roessel, T.: RESIST: A Recursive Test Pattern Generation Algorithm. IEEE Trans. on CAD 13(12), 1550–1561 (1994)Google Scholar
  7. 7.
    Tafertshofer, P., Ganz, A., Antreich, K.J.: IGRAINE–An Implication GRaph-bAsed engINE for Fast Implication, Justification, and Propagation. IEEE Trans. on CAD 19(8), 907–927 (2000)Google Scholar
  8. 8.
    Bhattacharya, D., et al.: Test Pattern Generation for Path Delay Faults using Binary Decision Diagrams. IEEE Trans. on Computers 44(3), 434–447 (1995)MATHCrossRefGoogle Scholar
  9. 9.
    Michael, M.K., Tragoudas, S.: Functions-based Compact TestPattern Generation for Path Delay Faults. IEEE Trans. on VLSI 13(8), 996–1001 (2005)CrossRefGoogle Scholar
  10. 10.
    Bryant, R.: Graph-based algorithms for Boolean function manipulation. IEEE Trans. on Computers C-35(8), 677–691 (1986)CrossRefGoogle Scholar
  11. 11.
    Cheng, C.A., Gupta, S.K.: Test generation for path delay faults based on satisfiability. In: IEEE Design Automation Conference (1996)Google Scholar
  12. 12.
    Yang, K., Cheng, K.T., Wang, L.C.: TranGen: A SAT-Based ATPG for Path-Oriented Transition Faults. In: ASP-DAC, pp. 92–97 (2004)Google Scholar
  13. 13.
    Singh, V., Inoue, M., Saluja, K.K., Fujiwara, H.: Instruction-Based Delay Fault Self-Testing of Processor Cores. In: IEEE International Conference on VLSI Design, pp. 933–938 (2004)Google Scholar
  14. 14.
    Lai, W.-C., Krstic, A., Cheng, K.-T.: Test Program Synthesis for Path Delay Faults in Microprocessor Cores. In: IEEE International Test Conference, pp. 1080–1089 (2000)Google Scholar
  15. 15.
    Gurumurthy, S., et al.: Automatic Generation of Instructions to Robustly Test Delay Defects in Processors. In: IEEE European Test Symposium, pp. 173–178 (2007)Google Scholar
  16. 16.
    Corno, F., et al.: Evolving Assembly Programs: How Games Help Microprocessor Validation. IEEE Trans. on Evolutionary Computation 9, 695–706 (2005)CrossRefGoogle Scholar
  17. 17.
    Sanchez, E., Schillaci, M., Sonza Reorda, M., Squillero, G.: An Enhanced Technique for the Automatic Generation of Effective Diagnosis-oriented Test Programs for Processors. In: IEEE Design, Automation and Test in Europe, pp. 1–6 (2007)Google Scholar
  18. 18.
    Schaffer, J.D.: Multiple Objective Optimization with Vector Evaluated Genetic Algorithms. In: Int’l Conf. on Genetic Algorithms and Their Applications, pp. 93–100 (1985)Google Scholar
  19. 19.
    Bernardi, P., et al.: On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores. In: IEEE European Test Symposium, pp. 179–184 (2007)Google Scholar
  20. 20.
    Bushnell, M.L., Agrawal, V.D.: Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits. Kluwer Academic Publishers, Dordrecht (2000)Google Scholar
  21. 21.
    CoelloCoello, C.A., Van Veldhuizenand, D.A., Lamont, G.B.: Evolutionary Algorithms for Solving Multi-Objective Problems. Kluwer Academic Publishers, Dordrecht (2002)Google Scholar
  22. 22.
    Huband, S., et al.: A Review of Multiobjective Test Problems and a Scalable Test Problem Toolkit. IEEE Trans. on Evolutionary Computation 10(5), 477–506 (2006)CrossRefGoogle Scholar
  23. 23.
    Padmanaban, S., Tragoudas, S.: Efficient Identification of (Critical) Testable Path Delay Faults Using Decisions Diagrams. IEEE Trans. on CAD 24(1), 77–87 (2005)Google Scholar
  24. 24.

Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • P. Bernardi
    • 1
  • K. Christou
    • 2
  • M. Grosso
    • 1
  • M. K. Michael
    • 2
  • E. Sánchez
    • 1
  • M. Sonza Reorda
    • 1
  1. 1.Dipartimento di Automatica e InformaticaPolitecnico di TorinoTorinoItaly
  2. 2.Department of Electrical and Computer EngineeringUniversity of CyprusNicosiaCyprus

Personalised recommendations