Hardware Accelerators for Cartesian Genetic Programming

  • Zdenek Vasicek
  • Lukas Sekanina
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4971)

Abstract

A new class of FPGA-based accelerators is presented for Cartesian Genetic Programming (CGP). The accelerators contain a genetic engine which is reused in all applications. Candidate programs (circuits) are evaluated using application-specific virtual reconfigurable circuit (VRC) and fitness unit. Two types of VRCs are proposed. The first one is devoted for symbolic regression problems over the fixed point representation. The second one is designed for evolution of logic circuits. In both cases a significant speedup of evolution (30–40 times) was obtained in comparison with a highly optimized software implementation of CGP. This speedup can be increased by creating multiple fitness units.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Zdenek Vasicek
    • 1
  • Lukas Sekanina
    • 1
  1. 1.Faculty of Information TechnologyBrno University of TechnologyBrnoCzech Republic

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