Hybrid-Mode Floating-Point FPGA CORDIC Co-processor
- Cite this paper as:
- Zhou J., Dou Y., Lei Y., Dong Y. (2008) Hybrid-Mode Floating-Point FPGA CORDIC Co-processor. In: Woods R., Compton K., Bouganis C., Diniz P.C. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2008. Lecture Notes in Computer Science, vol 4943. Springer, Berlin, Heidelberg
This paper presents a 32-bit floating-point CORDIC co- processor on FPGA, providing all known CORDIC functions. Firstly, we propose a hybrid-mode algorithm, combining hybrid rotation angle methods with argument reduction algorithm to reduce hardware area usage and meanwhile keep unlimited convergence domain for any floating-point inputs. And according to algorithm, the hybrid-mode CORDIC co-processor is organized into three phases, argument reduction, CORDIC calculation and normalization with 34 pipeline stages for FPGA implementation. The synthesis results show the clock frequency can reach 217MHz on Xilinx Virtex5 FPGA. Comparing to general-purpose microprocessor in three scientific program kernels, the CORDIC co-processor can guarantee at least 23-bit precision and achieve a maximum speedup of 47.6 times, 35.2 times in average.
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