An FPGA Run-Time Parameterisable Log-Normal Random Number Generator

  • Pedro Echeverría
  • David B. Thomas
  • Marisa López-Vallejo
  • Wayne Luk
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4943)

Abstract

Monte Carlo financial simulation relies on the generation of random variables with different probability distribution functions. These simulations, particularly the random number generator (RNG) cores, are computationally intensive and are ideal candidates for hardware acceleration. In this work we present an FPGA based Log-normal RNG ideally suited for financial Monte Carlo simulations, as it is run-time parameterisable and compatible with variance reduction techniques. Our architecture achieves a throughput of one sample per cycle with a 227.6 MHz clock on a Xilinx Virtex-4 FPGA.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Pedro Echeverría
    • 1
  • David B. Thomas
    • 2
  • Marisa López-Vallejo
    • 1
  • Wayne Luk
    • 2
  1. 1.Dept. de Ingeniería ElectrónicaUniversidad Politécnica de Madrid(Spain)
  2. 2.Dept. of ComputingImperial College London(United Kingdom)

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