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A Hardware Packet Re-Sequencer Unit for Network Processors

  • Michael Meitinger
  • Rainer Ohlendorf
  • Thomas Wild
  • Andreas Herkersdorf
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4934)

Abstract

Network Processors (NP) usually are designed as multi-processor systems with parallel packet processing. This parallelism may lead to flows with packets out-of-order when leaving the NP system. But packet reordering has a bad impact on network performance, especially when using the dominating TCP protocol. In this paper, we describe a Hardware Re-Sequencer Unit for Network Processors. Incoming packets will be tagged in the ingress path, preserving the packet order with flow granularity. An Aggregation Unit reorders the packet flows in the egress path if needed. In contrast to most other solutions the way of the packet through the NP system is dispensable, which enlarges design freedom in terms of e.g. load balancing. After explaining the general concept, a SystemC model is presented. Simulation results are used for dimensioning and a proof of concept with real traffic traces. General aspects concerning the implementation are discussed.

Keywords

Hash Function Collision Rate Network Processor Processing Engine Trace File 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Michael Meitinger
    • 1
  • Rainer Ohlendorf
    • 1
  • Thomas Wild
    • 1
  • Andreas Herkersdorf
    • 1
  1. 1.Technische Universität MünchenMunichGermany

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