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Performance Evaluation of Compiler Controlled Power Saving Scheme

  • Jun Shirako
  • Munehiro Yoshida
  • Naoto Oshiyama
  • Yasutaka Wada
  • Hirofumi Nakano
  • Hiroaki Shikano
  • Keiji Kimura
  • Hironori Kasahara
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4759)

Abstract

Multicore processors, or chip multiprocessors, which allow us to realize low power consumption, high effective performance, good cost performance and short hardware/software development period, are attracting much attention. In order to achieve full potential of multicore processors, cooperation with a parallelizing compiler is very important. The latest compiler extracts multilevel parallelism, such as coarse grain task parallelism, loop parallelism and near fine grain parallelism, to keep parallel execution efficiency high. It also controls voltage and clock frequency of processors carefully to reduce energy consumption during execution of an application program. This paper evaluates performance of compiler controlled power saving scheme which has been implemented in OSCAR multigrain parallelizing compiler. The developed power saving scheme realizes voltage/frequency control and power shutdown of each processor core during coarse grain task parallel processing. In performance evaluation, when static power is assumed as one-tenth of dynamic power, OSCAR compiler with the power saving scheme achieved 61.2 percent energy reduction for SPEC CFP95 applu without performance degradation on 4 processors and 87.4 percent energy reduction for mpeg2encode, 88.1 percent energy reduction for SPEC CFP95 tomcatv and 84.6 percent energy reduction for applu with real-time deadline constraint on 4 processors.

Keywords

Dynamic Power Static Schedule Multicore Processor Schedule Length Task Parallelism 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Jun Shirako
    • 1
  • Munehiro Yoshida
    • 1
  • Naoto Oshiyama
    • 1
  • Yasutaka Wada
    • 1
  • Hirofumi Nakano
    • 1
  • Hiroaki Shikano
    • 1
    • 2
  • Keiji Kimura
    • 1
  • Hironori Kasahara
    • 1
  1. 1.Dept. of Computer ScienceWaseda UniversityTokyoJapan
  2. 2.Central Research Laboratory, Hitachi, Ltd.Kokubunji-shiJapan

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