Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache
Aggressive function inlining can lead to significant improvements in execution time. This potential is reduced by extensive instruction cache (Icache) misses caused by subsequent code expansion. It is very difficult to predict which inlinings cause Icache conflicts, as the exact location of code in the executable depends on completing the inlining first. In this work we propose a new method for selective inlining called “Icache Loop Blockings” (ILB). In ILB we only allow inlinings that do not create multiple inlined copies of the same function in hot execution cycles. This prevents any increase in the Icache footprint. This method is significantly more aggressive than previous ones, experiments show it is also better.
Results on a server level processor and on an embedded CPU, running SPEC CINT2000, show an improvement of 10% in the execution time of the ILB scheme in comparison to other inlining methods. This was achieved without bloating the size of the hot code executed at any single point of execution, which is crucial for the embedded processor domain.
We have also considered the synergy between code reordering and inlining focusing on how inlining can help code reordering. This aspect of inlining has not been studied in previous works.
KeywordsBasic Block Call Graph Instruction Cache Call Site Cyclic Path
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- 1.Arnold, M., Fink, S., Sarkar, V., Sweeney, P.: A Comparative Study of Static and Profile-based Heuristics for Inlining. In: Proceedings of the ACM SIGPLAN Workshop on Dynamic and Adaptive Compilation and Optimization, pp. 52–64 (2000)Google Scholar
- 3.Ayers, A., Gottlieb, R., Schooler, R.: Aggressive Inlining. In: Proceedings of the 1997 ACM SIGPLAN Conference on Programming Language Design and Implementation, pp. 134–145 (June 1997)Google Scholar
- 4.Ball, J.E.: Program improvement by the selective integration of procedure calls. Technical report, PhD thesis, University of Rochester (1982)Google Scholar
- 7.Haber, G., Klausner, M., Eisenberg, V., Mendelson, B., Gurevich, M.: Optimization Opportunities Created by Global Data Reordering. In: CGO 2003. First International Symposium on Code Generation and Optimization (March 2003)Google Scholar
- 9.McFarling, S.: Procedure merging with instruction caches. In: Proceedings of the SIGPLAN Conference on Programming Language Design and Implementation, pp. 71–79 (June 1991)Google Scholar
- 10.Muth, R., Debray, S., Watterson, S.: ALTO: A Link-Time Optimizer for the Compaq Alpha. Technical Report 98-14, Dept. of Computer Science, The University of Arizona (December 1998)Google Scholar
- 11.Nahshon, I., Bernstein, D.: FDPR - A Post-Pass Object Code Optimization Tool (April 1996)Google Scholar
- 13.Schwarz, B., Debray, S., Andrews, G., Legendre, M.: PLTO: A Link-Time Optimizer for the Intel IA-32 Architecture. In: Proceedings of Workshop on Binary Rewriting (September 2001)Google Scholar
- 14.Way, T., Breech, B., Du, W., Stoyanov, V., Pollock, L.: Using path-pectra-based cloning in regional-based optimization for instruction level parallelism. In: Proceedings of the 14th International Conference on Parallel and Distributed Computing Systems, pp. 83–90 (2001)Google Scholar
- 15.Way, T., Pollock, L.: Evaluation of a Region-based Partial Inlining Algorithm for an ILP Optimizing Compiler. In: IASTED International Conference on Parallel and Distributed Computing and Systems (November 2002)Google Scholar
- 16.Zhao, P., Amaral, J.N.: To inline or not to inline? enhanced inlining decisions (2003)Google Scholar