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Compiler-Assisted Instruction Decoder Energy Optimization for Clustered VLIW Architectures

  • Rahul Nagpal
  • Y. N. Srikant
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4873)

Abstract

Traditionally, an instruction decoder is designed as a monolithic structure that inhibit the leakage energy optimization. In this paper, we consider a split instruction decoder that enable the leakage energy optimization. We also propose a compiler scheduling algorithm that exploits instruction slack to increase the simultaneous active and idle duration in instruction decoder. The proposed compiler-assisted scheme obtains a further 14.5% reduction of energy consumption of instruction decoder over a hardware-only scheme for a VLIW architecture. The benefits are 17.3% and 18.7% in the context of a 2-clustered and a 4-clustered VLIW architecture respectively.

Keywords

Schedule Algorithm Functional Unit Sleep Mode Leakage Energy Energy Overhead 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Rahul Nagpal
    • 1
  • Y. N. Srikant
    • 1
  1. 1.Department of Computer Science and Automation, Indian Institute of Science, BangaloreIndia

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