High Throughput Hardware Architecture for Motion Estimation with 4:1 Pel Subsampling Targeting Digital Television Applications

  • Marcelo Porto
  • Luciano Agostini
  • Leandro Rosa
  • Altamiro Susin
  • Sergio Bampi
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4872)

Abstract

Motion estimation is the most important and complex operation in video coding. This paper presents an architecture for motion estimation using Full Search algorithm with 4:1 Pel Subsampling, combined with SAD distortion criterion. This work is part of the investigations to define the future Brazilian system of digital television broadcast. The quality of the algorithm used was compared with Full Search through software implementations. The quality of 4:1 Pel Subsampling results was considered satisfactory, once it presents a SAD result with an impact inferior to 4.5% when compared with Full Search results. The designed hardware considered a search range of [-25, +24], with blocks of 16x16 pixels. The architecture was described in VHDL and mapped to a Xilinx Virtex-II Pro VP70 FPGA. Synthesis results indicate that it is able to run at 123,4MHz, reaching a processing rate of 35 SDTV frames (720x480 pixels) per second.

Keywords

Motion estimation hardware architecture FPGA design 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Marcelo Porto
    • 1
  • Luciano Agostini
    • 2
  • Leandro Rosa
    • 2
  • Altamiro Susin
    • 1
  • Sergio Bampi
    • 1
  1. 1.Microeletronics Groups (GME), UFRGS – Porto Alegre, RSBrazil
  2. 2.Group of Architectures and Integrated Circuits (GACI),UFPel – Pelotas, RSBrazil

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