A Floorplan-Based Power Network Analysis Methodology for System-on-Chip Designs

  • Shih-Hsu Huang
  • Chu-Liao Wang
  • Man-Lin Huang
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4808)

Abstract

In order to enable the single-pass design methodology, the planning of power distribution should be performed as early as possible. In this paper, we will tackle this problem at the floorplan stage. First, at the block level, we will present an effective method to model the behavior of local power network structure of a reused block. Next, at the full-chip level, we will present a floorplan-based power network analysis methodology for system-on-chip (SOC) designs. The proposed methodology works well because it uses suitable models to represent the local power networks of blocks according to the properties of blocks. Experimental data shows that the new modeling technique can identify the most critical drop voltage of a reused block and the floorplan-based analysis methodology is useful for the planning of power distribution network of a SOC design.

Keywords

Modeling Voltage Drop Power Consumption Reused Block 

References

  1. 1.
    Mitsuhashi, T., Kuh, E.S.: Power and Ground Network Topology Optimization for Cell-Based VLSIs. In: The Proc. of 29th Design Automation Conference, pp. 524–527 (1992)Google Scholar
  2. 2.
    Huang, S.H., Wang, C.L.: An Effective Floorplan-Based Power Distribution Network Design Methodology Under Reliability Constraints. In: Proc. of IEEE International Symposium on Circuits and Systems, vol. 1, pp. 353–356 (2002)Google Scholar
  3. 3.
    Rabaey, J.M., Pedram, M.: Low Power Design Methodologies. Kluwer Academic Publishers, Dordrecht (1996)Google Scholar
  4. 4.
    Yim, J.S., Bae, S.O., Kyung, C.M.: A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs. In: Proc. of Design Automation Conference, pp. 766–771 (1999)Google Scholar
  5. 5.
    Cho, D.S., Lee, K.H., Jang, G.J., Kim, T.S., Kong, J.T.: Efficient Modeling Techniques for IR drop Analysis in ASIC Designs. In: Proc. of the 12th Annual IEEE International ASIC/SOC Conference, pp. 64–68 (1999)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Shih-Hsu Huang
    • 1
  • Chu-Liao Wang
    • 1
  • Man-Lin Huang
    • 2
  1. 1.Department of Electronic Engineering, Chung Yuan Christian University, Chung Li, TaiwanR.O.C.
  2. 2.Office of Information Technology, Feng-Chia University, Tai Chung, TaiwanR.O.C.

Personalised recommendations