Design and Implementation of a High-Speed Reconfigurable Modular Arithmetic Unit

  • Wei Li
  • Zibin Dai
  • Tao Chen
  • Tao Meng
  • Xuan Yang
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4847)

Abstract

A high-performance and dynamic reconfigurable modular arithmetic unit is presented, which provides full support to modulo 28/216/232 addition and modulo232/ 216+1/232-1 multiplication operation. To save the hardware cost, we have adopted sharing technique to implement modular multiplication operation, and then optimized each critical block. The design has been realized using Altera’s FPGA. Synthesis, placement and routing of reconfigurable design have accomplished on 0.18μm SMIC process. The result proves that the propagation time of the critical path is 6.04ns. Compared with other designs, the reconfigurable modular arithmetic unit not only supports for diverse modular arithmetic in the block ciphers, but also provides IP Core for reconfigurable cryptographic system.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Booth, A.D.: A Signed Binary Multiplication Technique. Quarterly Journal of Mechanics and Applied Mathematics 4, 236–240 (1951)MATHCrossRefMathSciNetGoogle Scholar
  2. 2.
    Nan, Y.S., Chen, O.T.: Low-power multipliers by minimizing switching activities of partial products. In: IEEE International Symposium on Circuits and Systems[C]. IEEE Circuits and Systems Society, Arizona USA, pp. 93–96 (2002)Google Scholar
  3. 3.
    Ling, H.: High-Speed Binary Adder. IBM Journal of Research and Development 25, 156–166 (1981)CrossRefGoogle Scholar
  4. 4.
    Ying jie Qu.: The Research and Design of the Reconfigurable Logic for Cryptography[D]. In: Beijing University of Technology, Beijing China (2002)Google Scholar
  5. 5.
    Elbirt, A.J.: Reconfigurable Computing For Symmetric-Key Algorithms[D] Massachusetts: Electrical and Computer Engineering Department University of Massachusetts Lowell (2002)Google Scholar
  6. 6.
    Yu tai Ma: A Simplified Architecture for Modulo (2n + 1) Multiplication. IEEE Transactions on Computers 47 (1998)Google Scholar
  7. 7.
    MacSorley, O.L.: High-Speed Arithmetic in Binary Computers. Proceedings of the IRE 49, 67–91 (1961)CrossRefMathSciNetGoogle Scholar
  8. 8.
    Weinberger, A., Smith, J.L.: A One-Microsecond. Adder Using One-Megacycle Circuitry. IRE Transactions on Electronic Computers, 65–73 (1956)Google Scholar
  9. 9.
    Wallace, C.S.: A Suggestion for a Fast Multiplier. IEEE Transactions on Electronic Computers, 14–17 (1964)Google Scholar
  10. 10.
    Brent, P.R., Kung, T.H.: A regular layout for parallel adders. IEEE Trans. Comput. 32, 260–264 (1982)CrossRefMathSciNetGoogle Scholar
  11. 11.
    Kogge, P., Stone, H.: A parallel algorithm for the efficient solution. IEEE Trans. Comput. 22, 783–787 (1973)MathSciNetCrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Wei Li
    • 1
  • Zibin Dai
    • 1
  • Tao Chen
    • 1
  • Tao Meng
    • 1
  • Xuan Yang
    • 1
  1. 1.Institute of Electronic Technology, the PLA Information Engineering University, Zhengzhou 450004, Email: try_1118@163.comChina

Personalised recommendations