Modeling and Verification of Master/Slave Clock Synchronization Using Hybrid Automata and Model-Checking

  • Guillermo Rodriguez-Navas
  • Julián Proenza
  • Hans Hansson
Conference paper

DOI: 10.1007/978-3-540-76650-6_18

Part of the Lecture Notes in Computer Science book series (LNCS, volume 4789)
Cite this paper as:
Rodriguez-Navas G., Proenza J., Hansson H. (2007) Modeling and Verification of Master/Slave Clock Synchronization Using Hybrid Automata and Model-Checking. In: Butler M., Hinchey M.G., Larrondo-Petrie M.M. (eds) Formal Methods and Software Engineering. ICFEM 2007. Lecture Notes in Computer Science, vol 4789. Springer, Berlin, Heidelberg

Abstract

An accurate and reliable clock synchronization mechanism is a basic requirement for the correctness of many safety-critical systems. Establishing the correctness of such mechanisms is thus imperative. This paper addresses the modeling and formal verification of a specific fault-tolerant master/slave clock synchronization system for the Controller Area Network. It is shown that this system may be modeled with hybrid automata in a very natural way. However, the verification of the resulting hybrid automata is intractable, since the modeling requires variables that are dependent. This particularity forced us to develop some modeling techniques by which we translate the hybrid automata into single-rate timed automata verifiable with the model-checker Uppaal. These techniques are described and illustrated by means of a simple example.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Guillermo Rodriguez-Navas
    • 1
  • Julián Proenza
    • 1
  • Hans Hansson
    • 2
  1. 1.Departament de Matemàtiques i Informàtica, Universitat de les Illes BalearsSpain
  2. 2.Malardalen Real Time Research Center, Dept. of Computer Science and Electronics, Malardalen UniversitySweden

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