Modeling and Verification of Master/Slave Clock Synchronization Using Hybrid Automata and Model-Checking

  • Guillermo Rodriguez-Navas
  • Julián Proenza
  • Hans Hansson
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4789)

Abstract

An accurate and reliable clock synchronization mechanism is a basic requirement for the correctness of many safety-critical systems. Establishing the correctness of such mechanisms is thus imperative. This paper addresses the modeling and formal verification of a specific fault-tolerant master/slave clock synchronization system for the Controller Area Network. It is shown that this system may be modeled with hybrid automata in a very natural way. However, the verification of the resulting hybrid automata is intractable, since the modeling requires variables that are dependent. This particularity forced us to develop some modeling techniques by which we translate the hybrid automata into single-rate timed automata verifiable with the model-checker Uppaal. These techniques are described and illustrated by means of a simple example.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    ISO: ISO11898. Road vehicles - Interchange of digital information - Controller area network (CAN) for high-speed communication (1993)Google Scholar
  2. 2.
    Rodríguez-Navas, G., Bosch, J., Proenza, J.: Hardware Design of a High-precision and Fault-tolerant Clock Subsystem for CAN Networks. In: FeT 2003, Portugal (2003)Google Scholar
  3. 3.
    Rodríguez-Navas, G., Proenza, J., Hansson, H.: Using UPPAAL to Model and Verify a Clock Synchronization Protocol for the Controller Area Network. In: Proc. of the 10th IEEE International Conference on Emerging Technologies and Factory Automation, Catania, Italy (2005)Google Scholar
  4. 4.
    Henzinger, T.A., Kopke, P.W., Puri, A., Varaiya, P.: What’s decidable about hybrid automata? Journal of Computer and System Sciences 57(1), 94–124 (1998)MATHCrossRefMathSciNetGoogle Scholar
  5. 5.
    Daws, C., Yovine, S.: Two examples of verification of multirate timed automata with kronos. In: RTSS 1995, Pisa, Italy, pp. 66–75. IEEE Computer Society Press, Los Alamitos (1995)Google Scholar
  6. 6.
    Alur, R., Torre, S.L., Madhusudan, P.: Perturbed Timed Automata. In: Morari, M., Thiele, L. (eds.) HSCC 2005. LNCS, vol. 3414, pp. 70–85. Springer, Heidelberg (2005)Google Scholar
  7. 7.
    Behrmann, G., David, A., Larsen, K.G.: A tutorial on uppaal. In: Bernardo, M., Corradini, F. (eds.) SFM-RT 2004. LNCS, vol. 3185, pp. 200–236. Springer, Heidelberg (2004)Google Scholar
  8. 8.
    Rodriguez-Navas, G., Proenza, J., Hansson, H.: An UPPAAL Model for Formal Verification of Master/Slave Clock Synchronization over the Controller Area Network. In: Proc. of the 6th IEEE International Workshop on Factory Communication Systems, Torino, Italy, IEEE Computer Society Press, Los Alamitos (2006)Google Scholar
  9. 9.
    Alur, R., Madhusudan, P.: Decision problems for timed automata: A survey. In: Bernardo, M., Corradini, F. (eds.) SFM-RT 2004. LNCS, vol. 3185, pp. 200–236. Springer, Heidelberg (2004)Google Scholar
  10. 10.
    Tindell, K., Burns, A., Wellings, A.J.: Calculating Controller Area Network (CAN) Message Response Time. Control Engineering Practice 3(8), 1163–1169 (1995)CrossRefGoogle Scholar
  11. 11.
    Rufino, J., Veríssimo, P., Arroz, G., Almeida, C., Rodrigues, L.: Fault-tolerant broadcasts in CAN. In: The 28th IEEE International Symposium on Fault-Tolerant Computing, Munich, Germany (1998)Google Scholar
  12. 12.
    Proenza, J., Miro-Julia, J.: MajorCAN: A modification to the Controller Area Network to achieve Atomic Broadcast. In: IEEE Int. Workshop on Group Communication and Computations, Taipei, Taiwan (2000)Google Scholar
  13. 13.
    Henzinger, T.A., Pei-Hsin, H., Wong-Toi, H.: Algorithmic analysis of nonlinear hybrid systems. IEEE Transactions on Automatic Control 43(4), 540–554 (1998)MATHCrossRefGoogle Scholar
  14. 14.
    Schmuck, F., Cristian, F.: Continuous clock amortization need not affect the precision of a clock synchronization algorithm. In: PODC 1990, pp. 133–143. ACM Press, New York (1990)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Guillermo Rodriguez-Navas
    • 1
  • Julián Proenza
    • 1
  • Hans Hansson
    • 2
  1. 1.Departament de Matemàtiques i Informàtica, Universitat de les Illes BalearsSpain
  2. 2.Malardalen Real Time Research Center, Dept. of Computer Science and Electronics, Malardalen UniversitySweden

Personalised recommendations