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The Implementation and Evaluation of a Low-Power Clock Distribution Network Based on EPIC

  • Rong Ji
  • Xianjun Zeng
  • Liang Chen
  • Junfeng Zhang
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4672)

Abstract

The multiply clock domain (MCD) technique is a novel technique to compromising between synchronous systems and asynchronous systems to reduce the power. However, most present studies of MCD are based on superscalar architectures. In this paper, MCDE, a MCD technique based on explicitly parallel instruction computing (EPIC) architecture is designed and implemented to reduce the power of clock distribution network. In addition, a series of experiments have been done to evaluate it. The result of the experiments show that, using a MCDE clock network microarchitecture with a fine-grained adaptive dynamic adjustment algorithm, can effectively decrease the microprocessor power by 40%, compared with the original EPIC clock network microarchitecture.

Keywords

Asynchronous Communication Very Long Instruction Word Asynchronous System Synchronous System Annual International Symposium 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© IFIP International Federation for Information Processing 2007

Authors and Affiliations

  • Rong Ji
    • 1
  • Xianjun Zeng
    • 1
  • Liang Chen
    • 1
  • Junfeng Zhang
    • 1
  1. 1.School of Computer Science,National University of Defense Technology Changsha, Hunan, 410073China

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