Advertisement

How to Maximize the Potential of FPGA Resources for Modular Exponentiation

  • Daisuke Suzuki
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4727)

Abstract

This paper describes a modular exponentiation processing method and circuit architecture that can exhibit the maximum performance of FPGA resources. The modular exponentiation architecture proposed by us comprises three main techniques. The first technique is to improve the Montgomery multiplication algorithm in order to maximize the performance of the multiplication unit in FPGA. The second technique is to improve and balance the circuit delay. The third technique is to ensure and make fast the scalability of the effective FPGA resource. We propose a circuit architecture that can handle multiple data lengths using the same circuits. In addition, our architecture can perform fast operations using small-scale resources; in particular, it can complete 512-bit modular exponentiation in 0.26 ms by means of XC4VF12-10SF363, which is the minimum logic resources in the Virtex-4 Series FPGAs. Also, the number of SLICEs used is approx. 4000 to make a very compact design. Moreover, 1024-, 1536- and 2048-bit modular exponentiations can be processed in the same circuit with the scalability.

Keywords

Complementary Metal Oxide Semiconductor Modular Multiplication Modular Exponentiation Circuit Delay FPGA Resource 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    Montgomery, P.L.: Modular Multiplication without Trial Division. Mathematics of Computation 43(170), 519–521 (1985)CrossRefGoogle Scholar
  2. 2.
    Walter, C.D.: Systolic Modular Multiplication. IEEE Transactions on Computers 42(3), 376–378 (1993)CrossRefGoogle Scholar
  3. 3.
    Eldridge, S.E., Walter, C.D.: Hardware Implementation of Montgomery’s Modular Multiplication Algorithm. IEEE Transactions on Computers 42(6), 693–699 (1993)CrossRefGoogle Scholar
  4. 4.
    Orup, H.: Simplifying Quotient Determination in High-Radix Modular Multiplication. In: Proc. of the 12th IEEE Symposium on Computer Arithmetic, pp. 193–199 (1995)Google Scholar
  5. 5.
    Blum, T., Paar, C.: Montgomery Modular Exponentiation on Reconfigurable Hardware. In: Proc. of the 14th IEEE Symposium on Computer Arithmetic, pp. 70–77 (1999)Google Scholar
  6. 6.
    Walter, C.D: Montgomery’s Multiplication Technique: How to Make It Smaller and Faster. In: Koç, Ç.K., Paar, C. (eds.) CHES 1999. LNCS, vol. 1717, pp. 80–93. Springer, Heidelberg (1999)CrossRefGoogle Scholar
  7. 7.
    Tenca, A.F., Koç, Ç.K.: A Scalable Architecture for Montgomery Multiplication. In: Koç, Ç.K., Paar, C. (eds.) CHES 1999. LNCS, vol. 1717, pp. 94–108. Springer, Heidelberg (1999)CrossRefGoogle Scholar
  8. 8.
    Blum, T., Paar, C.: High-Radix Montgomery Modular Exponentiation on Reconfigurable Hardware. IEEE Transaction on Computers 50(7), 759–764 (2001)CrossRefGoogle Scholar
  9. 9.
    Tenca, A.F., Todorov, G., Koç, Ç.K.: High-Radix Design of a Scalable Modular Multiplier. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 185–201. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  10. 10.
    Nozaki, H., Motoyama, M., Shimbo, A., Kawamura, S.: Implementation of RSA Algorithm Based on RNS Montgomery Multiplication. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 364–376. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  11. 11.
    Tang, S.H., Tsui, K.S., Leong, P.H.W.: Modular Exponentiation using Parallel Multipliers. In: Proc. of the 2003 IEEE International Conference on Field Programmable Technology (FPT 2003), pp. 52–59 (2003)Google Scholar
  12. 12.
    Satoh, A., Takano, K.: A Scalable Dual-Field Elliptic Curve Cryptographic Processor. IEEE Transactions on Computers 52(4), 449–460 (2003)CrossRefGoogle Scholar
  13. 13.
    McIvor, C., McLoone, M., McCanny, J.V.: FPGA Montgomery Multiplier Architectures - A Comparsion. In: Proc. of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), pp. 279–282 (2004)Google Scholar
  14. 14.
    McIvor, C., McLoone, M., McCanny, J.V.: High-Radix Systolic Modular Multiplication on Reconfigurable Hardware. In: Proc. of the 2005 IEEE International Conference on Field Programmable Technology (FPT 2005), pp. 13–18 (2005)Google Scholar
  15. 15.
    Michalski, E.A., Buell, D.A.: A Scalable Architecture for RSA Cryptography on Large FPGAs. In: Proc. of the 16th IEEE International Conference on Field Programmable Logic and Applications (FPL 2006), pp. 145–152 (2006)Google Scholar
  16. 16.
    Kamala, R.V., Srinivas, M.B.: High-Throughput Montgomery Modular Multiplication. In: Proc. of the 14th IFIP International Conference on Very Large Scale Integration (VLSI-SoC 2006), pp. 58–62 (2006)Google Scholar
  17. 17.
    Sakiyama, K., Preneel, B., Verbauwhede, I.: A Fast Dual-Field Modular Arithmetic Logic Unit and Its Hardware Implementation. In: Proc. of the 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006), pp. 787–790 (2006)Google Scholar
  18. 18.
    Sakiyama, K., De Mulder, E., Preneel, B., Verbauwhede, I.: A Parallel Processing Hardware Architecture for Elliptic Curve Cryptosystems. In: Proc. of the 2006 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2006), vol. 3, pp. III-904-III-907 (2006)Google Scholar
  19. 19.
    The OpenCiphers Project (2005), http://openciphers.sourceforge.net/oc/
  20. 20.
    Knuth, D.E.: The Art of Computer Programming, Seminumerical Algorithms, 3rd edn., vol. 2. Addison-Wesley, Reading (1997)Google Scholar
  21. 21.
    Koç, Ç.K.: Analysis of Sliding Window Techniques for Exponentiation. Computers and Mathematics with Applications 30(10), 17–24 (1995)zbMATHCrossRefMathSciNetGoogle Scholar
  22. 22.
    Xilinx: Virtex-4 User Guide UG070 (v1.6)Google Scholar
  23. 23.
    Xilinx: XtremeDSP for Virtex-4 FPGAs User Guide UG073 (v2.3)Google Scholar
  24. 24.
    Xilinx: Virtex-4 Data Sheet: DC and Switching Characteristics DS302 (v2.0)Google Scholar
  25. 25.
    Xilinx: Alpha Blending Two Data Streams Using a DSP48 DDR Technique XAPP706 (v1.0)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Daisuke Suzuki
    • 1
  1. 1.Mitsubishi Electric Corporation, Information Technology R&D Center, 5-1-1 Ofuna Kamakura, Kanagawa, 247-8501Japan

Personalised recommendations