Cache Conscious Trees: How Do They Perform on Contemporary Commodity Microprocessors?

  • Kyungwha Kim
  • Junho Shim
  • Ig-hoon Lee
Conference paper

DOI: 10.1007/978-3-540-74472-6_15

Part of the Lecture Notes in Computer Science book series (LNCS, volume 4705)
Cite this paper as:
Kim K., Shim J., Lee I. (2007) Cache Conscious Trees: How Do They Perform on Contemporary Commodity Microprocessors?. In: Gervasi O., Gavrilova M.L. (eds) Computational Science and Its Applications – ICCSA 2007. ICCSA 2007. Lecture Notes in Computer Science, vol 4705. Springer, Berlin, Heidelberg

Abstract

Some index structures have been redesigned to minimize the cache misses and improve their CPU cache performances. The Cache Sensitive B+-Tree and recently developed Cache Sensitive T-Tree are the most well-known cache conscious index structures. Their performance evaluations, however, were made in single core CPU machines. Nowadays even the desktop computers are equipped with multi-core CPU processors. In this paper, we present an experimental performance study to show how cache conscious trees perform on different types of CPU processors that are available in the market these days.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Kyungwha Kim
    • 1
  • Junho Shim
    • 1
  • Ig-hoon Lee
    • 2
  1. 1.Dept of Computer Science, Sookmyung Women’s UniversityKorea
  2. 2.Prompt Corp., SeoulKorea

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