A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations

  • Francesco Centurelli
  • Luca Giancane
  • Mauro Olivieri
  • Giuseppe Scotti
  • Alessandro Trifiletti
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4644)


Process variations are becoming a paramount design problem in nano-scale VLSI. We present a framework for the statistical model of logic gates that describes both inter-die and intra-die variations of performance parameters such as propagation delay and leakage currents. This allows fast but accurate behavioral-level Monte-Carlo simulations, that could be useful for full-custom digital design optimization and yield prediction, and enables the development of a yield-aware digital design flow. The model can incorporate correlation between mismatch parameters and dependence on distance and position, and can be extracted by fitting of Monte-Carlo transistor level simulations. An example implementation using Verilog-A hardware description language in Cadence environment is presented.


Leakage Current Logic Gate Stochastic Variable Yield Prediction NAND Gate 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Francesco Centurelli
    • 1
  • Luca Giancane
    • 1
  • Mauro Olivieri
    • 1
  • Giuseppe Scotti
    • 1
  • Alessandro Trifiletti
    • 1
  1. 1.Dipartimento di Ingegneria Elettronica, Università di Roma "La Sapienza", Via Eudossiana 18, 00184 RomaItaly

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