Advertisement

An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture

  • Julien Delorme
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4644)

Abstract

Complex application specific SoC are often based on the Network-on-Chip (NoC) approach. NoC are under investigation since several years and many architectures have been proposed. Generic NoC are often proposed with their synthesis tool in order to rapidly tailor a solution for a specific application implementation. The optimized mapping of cores on a NoC and the optimized NoC configuration in terms of topology, FIFO and link sizes for instance is a new research area which is investigated deeply now. Validation and evaluation of solutions is often conducted through simulations. Comparisons between proposed optimization approaches is difficult as they use their own evaluative application. Benchmarking is a classical solution to normalize comparisons. We are proposing in this paper a complete design flow which allow to make an automatic Algorithm Architecture Adequation (AAA) onto a NoC architecture. This flow is based on a SystemC model simulation at TLM level. We illustrate these design flow with a benchmark of an 4G radiocommunication application.

Keywords

Network Interface OFDM Symbol Hardware Constraint 4MORE Project Propose Optimization Approach 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    de Micheli, G., Benini, L.: Networks on chip: A new paradigm for systems on chip design. In: DATE ’02: Proceedings of the conference on Design, automation and test in Europe, p. 418. IEEE Computer Society Press, Washington, DC, USA (2002)Google Scholar
  2. 2.
    Third, M.M.R., Jantsch, A.: Evaluating noc communication backbones with simulation. In: IEEE NorChip Conference, November 2003, IEEE Computer Society Press, Los Alamitos (2003)Google Scholar
  3. 3.
    Durand, Y., Bernard, C., Lattard, D.: Faust: On-chip distributed architecture for a 4g baseband modem soc. In: IPSOC 2005 (December 2005)Google Scholar
  4. 4.
    Felperin, P.R.S., Upfal, E.: A theory of wormhole routing in parallel computers. IEEE Transactions on Computers, 704–713 (1996)Google Scholar
  5. 5.
    Glass, C.J., Ni, L.M.: The turn model for adaptive routing, vol. 41(5), pp. 874–902. ACM Press, New York, USA (1994)Google Scholar
  6. 6.
    Hansson, A., Goossens, K., Radulescu, A.: A unified approach to constrained mapping and routing on network-on-chip architectures. In: CODES+ISSS 2005: Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pp. 75–80. ACM Press, New York, USA (2005)CrossRefGoogle Scholar
  7. 7.
    Goossens, K., Dielissen, J., Gangwal, O.P., Pestana, S.G., Radulescu, A., Rijpkema, E.: A design flow for application-specific networks on chip with guaranteed performance to accelerate soc design and verification. In: DATE 2005: Proceedings of the conference on Design, Automation and Test in Europe, pp. 1182–1187. IEEE Computer Society Press, Washington, DC, USA (2005)Google Scholar
  8. 8.
    Hu, J., Marculescu, R.: Exploiting the routing flexibility for energy/performance aware mapping of regular noc architectures. In: DATE 2003: Proceedings of the conference on Design, Automation and Test in Europe, p. 10688. IEEE Computer Society Press, Washington, DC, USA (2003)Google Scholar
  9. 9.
    Hu, J., Marculescu, R.: Energy-aware mapping for tile-based noc architectures under performance constraints. In: Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific, pp. 233–239. IEEE Computer Society Press, Washington, DC, USA (2003)Google Scholar
  10. 10.
    Hu, R.M.J.: Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints. In: DATE 04: Proceedings of the conference on Design, automation and test in Europe, p. 10234 (2004)Google Scholar
  11. 11.
    Chouly, A.B.A., Jourdan, S.: Orthogonal multicarrier techniques applied to direct sequence spread spectrum cdma systems. In: GLOBECOM 1993, pp. 1723–1728 (2005)Google Scholar
  12. 12.
    Rijpkema, E., Goossens, K.G.W., Radulescu, A., Dielissen, J., van Meerbergen, J., Wielage, P., Waterlander, E.: Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip. In: DATE 2003: Proceedings of the conference on Design, Automation and Test in Europe, p. 10350. IEEE Computer Society Press, Washington, DC, USA (2003)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Julien Delorme
    • 1
  1. 1.INSA/IETR Laboratory, 20 avenue des Buttes de Coesmes, 35043 Rennes CedexFrance

Personalised recommendations