Using Wavelet Transform and Partial Distance Search to Implement kNN Classifier on FPGA with Multiple Modules
This paper presents a novel algorithm of using wavelet transform and partial distance search (PDS) to realize the kNN classifier on field programmable gate array (FPGA) with multiple modules. The algorithm identifies first k closest vectors in the design set of a kNN classifier for each input vector by performing the PDS in the wavelet domain, and allows concurrent classification of different input vectors for further computation acceleration by employing multiple-module PDS. For the effective reduction of the area complexity and computation latency, we proposed a novel PDS algorithm well-suited for hardware implementation and also employ subspace search, bitplane reduction and multiple-coefficient accumulation techniques. The proposed realization has been embedded in a softcore CPU for physical performance measurements. Experimental results show that the proposed realization not only provides a cost-effective solution to the FPGA implementation of kNN classification systems, but also meets both high throughput and low area cost.
KeywordsFPGA Implementation kNN Classifier Partial Distance Search Pattern Recognition Nonparametric Classification
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